A 6-bit 10-GS/s 63-mW 4x TI time-domain interpolating flash ADC in 65-nm CMOS

Oh, Dong-Ryeol; Kim, Jong-In; Seo, Min-Jae; Kim, Jin-Gwang; Ryu, Seung‐Tak

doi:10.1109/esscirc.2015.7313892

Cited by 12 publications

(9 citation statements)

References 5 publications

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“…Therefore, comparison of this work with them may not be fair. [2] and [4] uses flash ADC cores, however, the design tech-nology and the resolution are different than this work. In this design, 10 GS/s sampling rate is achieved in 0.25 µm CMOS technology.…”

Section: Post-layout Simulation Resultsmentioning

confidence: 96%

“…This work consumes more power, which may be considered as a disadvantage. [2] and [4] include a calibration circuitry unlike this design. In terms of layout area, it is not fair to make comparison since having lower resolution.…”

Section: Post-layout Simulation Resultsmentioning

confidence: 99%

“…New generation wired or wireless communication systems, high performance oscilloscopes, software defined radio, optical communication systems, low noise amplifiers (LNAs), and mixers require higher bandwidth, operating frequency, dynamic range, and sampling rates [1][2][3][4][5]. These developments undoubtedly increase the importance of high resolution and high sampling rate ADCs.…”

Section: Introductionmentioning

confidence: 99%

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A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology

Aytar

Tangel

Afacan

2017

Journal of Electrical Engineering

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This paper presents design and simulation of a 4-bit 10 GS/s time interleaved ADC in 0.25 micrometer CMOS technology. The designed TI-ADC has 4 channels including 4-bit flash ADC in each channel, in which area and power efficiency are targeted. Therefore, basic standard cell logic gates are preferred. Meanwhile, the aspect ratios in the gate designs are kept as small as possible considering the speed performance. In the literature, design details of the timing control circuits have not been provided, whereas the proposed timing control process is comprehensively explained and design details of the proposed timing control process are clearly presented in this study. The proposed circuits producing consecutive pulses for timing control of the input S/H switches (ie the analog demultiplexer front-end circuitry) and the very fast digital multiplexer unit at the output are the main contributions of this study. The simulation results include +0.26/−0.22 LSB of DNL and +0.01/−0.44 LSB of INL, layout area of 0.27 mm2, and power consumption of 270 mW. The provided power consumption, DNL and INL measures are observed at 100 MHz input with 10 GS/s sampling rate.

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Section: Post-layout Simulation Resultsmentioning

confidence: 96%

Section: Post-layout Simulation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology

Aytar

Tangel

Afacan

2017

Journal of Electrical Engineering

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“…Introduction: As CMOS technology improves with reduced supply voltages, time-domain signal processing utilising voltage-to-time converters (VTCs) has been exploited in various ADC architectures, including flash and sub-ranging ADCs [1][2][3][4]. While a VTC converts the input voltage into time difference, the precharging (reset) and discharging (conversion) operations conducted in every clock cycle are the major sources of power consumption.…”

mentioning

confidence: 99%

Power‐efficient flash ADC with complementary voltage‐to‐time converter

Moon

et al. 2017

Electron. lett.

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A power-efficient complementary voltage-to-time converter (CVTC) is proposed for a flash ADCs. The alternating reset direction according to the signal development direction reduces the power consumed by the reset operation and the operational frequency of the CVTC is effectively reduced by half. Accordingly, the logic circuits following the CVTC work in a time-interleaved manner, resulting in significant power saving. A 5-bit 2.5 GS/s flash ADC designed for a 40 nm CMOS process shows a 27% power reduction over the conventional voltage-to-time conversion-based flash ADC.

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“…2 to 5GHz range will serve as a boon from the applications perspective. There have been implementations of such multi-GSPS ADCs working around 5 to 10 GSPS range using the Complementary Metal Oxide Semiconductor technology with various architectures such as pipelined, time-interleaving, Successive Approximation Register (SAR) and flash with flash being the most popular choice of architecture [1][2][3][4][5].…”

Section: Introductionmentioning

confidence: 99%

Design and Simulation of a 10 GSPS Low Power Sample and Hold Less Analog to Digital Converter Using Carbon Nanotube Field Effect Transistors

Takalikar¹,

Narkhede²

2017

IJME

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A 5 bit sample-and-hold less pipelined ADC is presented for high speed and low power applications. The architecture is designed using 32nm CNFET model in Hspice and simulation is carried out at 10 GSPS sampling rate. From the simulation results, the SNDR is found out to be 32.89dB at Nyquist frequency and the ERBW is found to be 3GHz from 2 to 5GHz in which ENOB is guaranteed to be above 4.6. The average power consumed is 5.031mW for a supply voltage of 1.4V and FoM is 53.32fJ/step.

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A 6-bit 10-GS/s 63-mW 4x TI time-domain interpolating flash ADC in 65-nm CMOS

Cited by 12 publications

References 5 publications

A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology

A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology

Power‐efficient flash ADC with complementary voltage‐to‐time converter

Design and Simulation of a 10 GSPS Low Power Sample and Hold Less Analog to Digital Converter Using Carbon Nanotube Field Effect Transistors

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