Power‐efficient flash ADC with complementary voltage‐to‐time converter

Abstract

A power-efficient complementary voltage-to-time converter (CVTC) is proposed for a flash ADCs. The alternating reset direction according to the signal development direction reduces the power consumed by the reset operation and the operational frequency of the CVTC is effectively reduced by half. Accordingly, the logic circuits following the CVTC work in a time-interleaved manner, resulting in significant power saving. A 5-bit 2.5 GS/s flash ADC designed for a 40 nm CMOS process shows a 27% power reduction over the conventional voltage-to-time conversion-based flash ADC.

International Journal of Electronics and Telecommunications

“…The Comparator forms the main building block of FLASH ADC. The input analog signal is compared with a reference voltage in the comparator and produces a digital signal [7][8][9]. When the input voltage is greater than the reference voltage the comparator output is logic 1.…”