A 6 bit 10 GS/s TI-SAR ADC With Low-Overhead Embedded FFE/DFE Equalization for Wireline Receiver Applications

With the great improvement in data transmission rate requirements, the analog-to-digital converter (ADC)-based wireline receiver has received more attention due to its flexible and powerful equalization capability. Time-interleaved ADC (TI-ADC) is the most commonly used architecture in high-speed ADC-based receivers. One of the major challenges in TI-ADC is the timing mismatch between the parallel sub-ADCs. The traditional skew detection and calibration circuits consume substantial power and area of the receiver system. In this article, we propose a novel calibration method using the autocorrelation principle combined with an existing Mueller–Müller clock and data recovery circuit (MM-CDR). This new method reuses the existing error-direction information of the MM-CDR in the ADC-based wireline receiver and combines the autocorrelation principle to obtain the timing mismatch information in the TI-ADC without adding an additional skew deviation extraction circuit, which greatly reduces the area and power consumption. In order to demonstrate the effectiveness and superiority of our skew calibration method, we designed a complete ADC-based wireline receiver circuit using the 28 nm CMOS technology. The simulation results show that our proposed calibration method could obtain 0.193 sensitivity per 1% skew, which was superior to traditional calibration methods. To verify the speed and accuracy of the convergence of our calibration method, the initial skews were set to +0.4 ps, +0.2 ps, −0.59 ps, and 0 ps for our 4 × 8 TI-ADC; the spurious free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) of the ADC were increased from 37.24 dB and 31.28 dB to 48.07 dB and 34.56 dB, respectively, after timing calibration with a 50 fs step. In order to compare the area and power consumption required by different skew calibration methods, we synthesized the expressions of various methods using the 28 nm CMOS technology, and the area and power consumption of our proposed skew calibration loop were 695 μm2 and 0.126 mW, respectively, which were the smallest among these methods.

Section: A Sinewave-input Fft-based Foreground Methodsmentioning

confidence: 99%

Section: Timing Mismatch Calibrationmentioning

confidence: 99%

A Novel Autocorrelation Combined MM-CDR Time-Interleaved ADC Timing Calibration in 28 nm CMOS Technology

Feng

Chi

et al. 2022

“…However, many comparators required in the flash ADC and the burden on the offset calibration circuits for them directly affect the area and power consumption of the flash-based TI ADCs [6][7][8][9][10]. Recent studies on tens of GS/s TI ADCs have shown that the conversion speed of the SAR ADCs, used as the sub-ADC of the TI ADC, has been improved to the GHz level thanks to the advanced CMOS process [11][12][13][14]. However, the SAR 2 of 19 ADC requires not only the high-speed design for the comparator and logic corresponding to the number of conversion cycles, but also the management of internal clock signals for the comparator.…”

Section: Introductionmentioning

confidence: 99%

A 6-Bit 20 GS/s Time-Interleaved Two-Step Flash ADC in 40 nm CMOS

2022

A 6-bit 20 GS/s 16-channel time-interleaved (TI) analog-to-digital converter (ADC) using a two-step flash ADC with a sample-and-hold (S/H) sharing technique and a gain-boosted voltage-to-time converter (VTC) is presented for high-speed wireline communication systems. By sharing one S/H between coarse and fine stages in the two-step flash ADC, the input bandwidth as well as area and power efficiency can be improved without a gain error between coarse and fine ADCs. Thanks to an eight-time interpolation using the gain-boosted VTC, the fine ADC has a small gate capacitance without a speed penalty, even in a small input voltage range. A prototype ADC implemented in a 40 nm CMOS process occupies a 0.1 mm2 active area. The measured differential non-linearity (DNL) and integral non-linearity (INL) after offset and gain calibrations were 0.45 and 0.39 least significant bit (LSB), respectively. With a 9.042 GHz input, the measured signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) were 30.12 and 40.23 dB, respectively. The small input capacitance of the sub-ADC enables a power-efficient track-and-hold amplifier (THA), resulting in a power consumption of 56.2 mW under a supply voltage of 0.9 V. The prototype ADC achieves a figure of merit (FoM) of 107.4 fJ/conversion-step at 20 GS/s.

“…Due to the rapid growth of wireless and wireline communications, high-speed broadband ADC with low distortion is required. For example, 10~30 GS/s ADCs with 6~8-bit resolution are demanded in the PAM-4 wireline receiver [1][2][3]. The sample-and-hold amplifier (SHA) at the front end of an ADC is a key block, because it can not only alleviate the bandwidth requirement for the following blocks, but also eliminate the influence of clock jitter and signal skew in the following ADCs [4].…”

Section: Introductionmentioning

confidence: 99%

A Low-Distortion 20 GS/s Four-Channel Time-Interleaved Sample-and-Hold Amplifier in 0.18 μm SiGe BiCMOS

Ding

Zheng

et al. 2019

This paper presents a 20 GS/s four-channel time-interleaved sample-and-hold amplifier (SHA), which aims to improve the harmonic distortion performance, eliminate the common-mode voltage fall in track-to-hold transition, and solve the difficulty of timing mismatch calibration among different sampling channels. In data path, the harmonic distortion of the track-hold switch is optimized by introducing a distortion-improving resistor into the switched emitter follower. The common-mode voltage fall is eliminated by an inserted delay-regulating resistor. Additionally, broadband data buffers are utilized to further guarantee a wide bandwidth. In clock path, an interpolator-based phase regulator in analog domain is implemented to calibrate the timing mismatch, hence avoiding the large area cost and complicated algorithm in the digital domain. Fabricated in a 0.18 μm SiGe BiCMOS process, the experimental results show that the SHA achieves a bandwidth of 16 GHz and a total harmonic distortion of −39.6 to approximately −51.8 dB with a −3 dBm input. By applying the proposed sampling phase regulator, the timing mismatch can be optimized to satisfy the requirement of 6-bit resolution at a 4 × 5 GS/s sampling rate. The proposed SHA shows prominent performance on both bandwidth and linearity, which makes it suitable for ultra-high-speed communication networks.