A 6-bit Fully Binary Digital-to-Analog Converter in 0.25-$\mu{\hbox {m}}$ SiGe BiCMOS for Optical Communications

Khafaji, Mohammad Mahdi; Gustat, H.; Sedighi, Behnam; Ellinger, Frank; Scheytt, J. Christoph

doi:10.1109/tmtt.2011.2161879

Cited by 13 publications

(13 citation statements)

References 21 publications

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“…The chosen rate here is 32 GSps with eight parallel bit streams. This is in-line with the state-of-the-art DACs concerning optical communications [8,9]. It also offers some margin to test the developed DACs for future OFDM optical communications, as they do not require more than 8 bit resolution [10,11].…”

Section: Introductionsupporting

confidence: 76%

A 32 GSps multiplexer with 1 kbit memory for arbitrary signal generation for testing digital‐to‐analogue converters

Khafaji

Carta

Tittelbach‐Helmrich

et al. 2014

IET Circuits, Devices & Systems

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Recent high-speed digital-to-analogue converters (DACs) cannot be easily characterised at their highest rate because of the very high cost of commercially available bit-error rate testers at the required DACs rate. Among possible solutions, an inexpensive approach is the use of a multiplexer (MUX) with built-in memory to provide the required bit stream for one input bit of the DAC. This work presents a half-rate 32 GSps MUX with 1 kbit built-in memory as a part of an arbitrary test signal generator for a DAC. The proposed system can be used to test DACs developed for future OFDM optical communications. Here, a bipolar-CMOS (BiCMOS) 0.25 μm SiGe process is utilised. One challenge is to optimise the power dissipation of such an MUX which requires employing several techniques. At the system level, the conventional tree structure was avoided because of the high number of latches required to re-time the clock and data signals. At the highest rates, a multiphase-clock architecture was utilised which halves the number of latches compared with a tree structure. The phase margin of the multiphase-clock structure is enhanced in this work. At lower rates, a one-stage MUX architecture was used which also halves the number of latches. Additionally, the latency between the analogue-digital interface is discussed. All the implemented circuits including the biasing of the whole chip and its routing are presented. The design and optimisation of the clock driver for low-power functionality is discussed. Measurement results show proper operation at 32 GSps. The total power dissipation is 875 mW, which is the lowest power among the designs usable for DAC testing and at the same rate class.

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Section: Introductionsupporting

confidence: 76%

A 32 GSps multiplexer with 1 kbit memory for arbitrary signal generation for testing digital‐to‐analogue converters

Khafaji

Carta

Tittelbach‐Helmrich

et al. 2014

IET Circuits, Devices & Systems

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“…For regular R L values, these factors put an upper boundary on the DAC resolution in a high speed BJT design, according to (12). One challenge here is to implement a current switch which exhibits high ω T at low output currents [18]. V. CONCLUSIONS Compact equations have been derived to review the SFDR and NOB limitations of high speed DACs using single transistor as well as cascode switching cells.…”

Section: Discussionmentioning

confidence: 99%

SFDR considerations for current steering high-speed digital to analog converters

Khafaji

Scheytt

Jorges

et al. 2012

2012 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)

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In this paper the spurious free dynamic range (SFDR) of a current steering digital-to-analog converter (DAC) is related to the process parameters used for its implementation. It is shown that the realization of such DACs in advanced processes provides power and area reduction combined with faster signaling. However, it is very challenging to improve the SFDR at a certain given output swing and sampling frequency. It is demonstrated that the SFDR can be doubled by using an optimized cascode switch. It is also concluded that compared to MOSFET based approaches higher sampling frequencies can be achieved by bipolar transistor based DACs if the SFDR and transition frequency are fixed. The reason is the higher Early voltage of bipolar transistors.

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“…Transmission Gate (TG) is used in digital CMOS circuit design to pass or not pass a signal. [23][24][25] In other words, it acts like switch. The gate is made up of the parallel connection of p-and n-channel MOSFET.…”

Section: R2r D/a Converter Using Tgmentioning

confidence: 99%

Simulation & performance analysis of various R2R D/A converter using various topologies

Whig

Ahmad

Priyam

2018

IRATJ

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This paper presents the study of R2R D/A converter using various topologies like CMOS, Transmission Gates (TG) and OP-AMP. For the sake of simplicity 4 bit input is taken. The R2R D/A converter consist of only two values of resistor R & 2R. By using the repetitive arrangement of precision resistor network in a ladder. The simulation of the R2R D/A converter has been done on the TANNER-EDA T-SPICE and the circuit verification has been done on S-EDIT on TANNER-EDA software package. Simulation results are included to demonstrate the results. The outcomes of simulation are fairly in agreement with the theoretical estimation.

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A 6-bit Fully Binary Digital-to-Analog Converter in 0.25-$\mu{\hbox {m}}$ SiGe BiCMOS for Optical Communications

Cited by 13 publications

References 21 publications

A 32 GSps multiplexer with 1 kbit memory for arbitrary signal generation for testing digital‐to‐analogue converters

A 32 GSps multiplexer with 1 kbit memory for arbitrary signal generation for testing digital‐to‐analogue converters

SFDR considerations for current steering high-speed digital to analog converters

Simulation & performance analysis of various R2R D/A converter using various topologies

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