A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers

Ishibashi, Koji; Takasugi, Kashiya; Komiyaji, K.; Toyoshima, Hideo; Yamanaka, Toshiaki; Fukami, Akira; Hashimoto, Norikazu; Ohki, N.; Shimizu, Akihiro; Hashimoto, Takayuki; Nagano, Takahiro; Nishida, Takashi

doi:10.1109/4.375969

Cited by 30 publications

(2 citation statements)

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“…One effective solution for accurate powerefficient high-speed sensing is the use of current sense amplifier. The current sense amplifier operation is based on the bitlines differential current, created due to a cell read operation, irrespective of bitlines voltage swing [12,13,14,15]. Nonetheless, the limited cell drivability and the column leakage current compromise the advantages of the current sense amplifiers.…”

Section: B Conventioanl Sense Amplifer Schemesmentioning

confidence: 99%

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A body-bias based current sense amplifier for high-speed low-power embedded SRAMs

Shakir

Sachdev

2014

2014 27th IEEE International System-on-Chip Conference (SOCC)

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Advances in CMOS technology has resulted in ever growing demand in on-chip high-density low-power SRAMs. A miniaturized low voltage-operated SRAM cell ability to generate adequate swing on heavily loaded bitlines is a serious design concern. In addition, Process, Voltage and Temperature variation PVTs in nanometric CMOS regime results in significant SARM cell parameters deviation. Sense amplifier offset voltage is the bottleneck in successful SRAM read operation. Therefore, offset voltage-insensitive current sense amplifiers are usually adopted in high performance SARMs. Read-assist techniques start to merge in the sate-of-the-art highspeed low-power SRAMs. This work presents a new high speed low power current sense amplifier. The proposed scheme utilizes transistor body bias to control the bitlines differential current. Monte Carlo simulations are conducted to validate the proposed scheme performance in presence of PVTs variations. Compared to conventional schemes, up to 28% in read failures reduction at 25mV bitlines swing is achieved. In addition, a 41% improvement in speed and up to 2.5X times less bitlines swing requirement at 0.6 V operating voltage is also verified. Key words: Current sense Amplifier, read assist, soft failure, low power SRAM, and body bias.I.

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Section: B Conventioanl Sense Amplifer Schemesmentioning

confidence: 99%

“…However, given the stringent high density SRAM constraints, reducing the sense amplifier offset voltage plays a key role in SRAM's FIR reduction. The use of offset voltage-insensitive current sense amplifiers is a prominent solution to overcome the speed limitations while maintaining a high degree of integration [10].…”

Section: Introductionmentioning

confidence: 99%