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Embedded memories comprise over half the die area in modern SOC ICs. These circuits enable large gains in performance, however they bring with them many challenges. As CMOS technology scales deep into the nano-metric region the size and density of embedded memories are increasing, both of which result in increased challenges for designers. This paper describes the design challenges intrinsic to the implementation of embedded memories in modern nanometric CMOS processes.

Advances in CMOS technology has resulted in ever growing demand in on-chip high-density low-power SRAMs. A miniaturized low voltage-operated SRAM cell ability to generate adequate swing on heavily loaded bitlines is a serious design concern. In addition, Process, Voltage and Temperature variation PVTs in nanometric CMOS regime results in significant SARM cell parameters deviation. Sense amplifier offset voltage is the bottleneck in successful SRAM read operation. Therefore, offset voltage-insensitive current sense amplifiers are usually adopted in high performance SARMs. Read-assist techniques start to merge in the sate-of-the-art highspeed low-power SRAMs. This work presents a new high speed low power current sense amplifier. The proposed scheme utilizes transistor body bias to control the bitlines differential current. Monte Carlo simulations are conducted to validate the proposed scheme performance in presence of PVTs variations. Compared to conventional schemes, up to 28% in read failures reduction at 25mV bitlines swing is achieved. In addition, a 41% improvement in speed and up to 2.5X times less bitlines swing requirement at 0.6 V operating voltage is also verified. Key words: Current sense Amplifier, read assist, soft failure, low power SRAM, and body bias.I.