Integrated read assist-sense amplifier scheme for high performance embedded SRAMs

Shakir, Tahseen; Rennie, D.; Sachdev, Manoj

doi:10.1109/mwscas.2010.5548581

Cited by 3 publications

(2 citation statements)

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“…The main idea of the read-assist techniques is to provide another current path to discharge the bitline during read operation. Read-assist process is accomplished by adding positive feedback mechanism in the sense amplifier circuit [9] or by direct bitline/sense amplifier coupling [2]. Other read-assist techniques are used by adapting cell's controlling signals level.…”

Section: B Conventioanl Sense Amplifer Schemesmentioning

confidence: 99%

“…Using dedicated read port is also used to control the cell drivability by sizing up specific transistors [6, 7, and 8]. Cell level and array level read-assist techniques are recently reported to support the cell drivability [2,9]. However, given the stringent high density SRAM constraints, reducing the sense amplifier offset voltage plays a key role in SRAM's FIR reduction.…”

Section: Introductionmentioning

confidence: 99%

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A body-bias based current sense amplifier for high-speed low-power embedded SRAMs

Shakir

Sachdev

2014

2014 27th IEEE International System-on-Chip Conference (SOCC)

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Advances in CMOS technology has resulted in ever growing demand in on-chip high-density low-power SRAMs. A miniaturized low voltage-operated SRAM cell ability to generate adequate swing on heavily loaded bitlines is a serious design concern. In addition, Process, Voltage and Temperature variation PVTs in nanometric CMOS regime results in significant SARM cell parameters deviation. Sense amplifier offset voltage is the bottleneck in successful SRAM read operation. Therefore, offset voltage-insensitive current sense amplifiers are usually adopted in high performance SARMs. Read-assist techniques start to merge in the sate-of-the-art highspeed low-power SRAMs. This work presents a new high speed low power current sense amplifier. The proposed scheme utilizes transistor body bias to control the bitlines differential current. Monte Carlo simulations are conducted to validate the proposed scheme performance in presence of PVTs variations. Compared to conventional schemes, up to 28% in read failures reduction at 25mV bitlines swing is achieved. In addition, a 41% improvement in speed and up to 2.5X times less bitlines swing requirement at 0.6 V operating voltage is also verified. Key words: Current sense Amplifier, read assist, soft failure, low power SRAM, and body bias.I.

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Section: B Conventioanl Sense Amplifer Schemesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%