Statistical SRAM Read Access Yield Improvement Using Negative Capacitance Circuits

Mostafa, Hassan; Anis, Mohab; Elmasry, M.I.

doi:10.1109/tvlsi.2011.2178046

Cited by 10 publications

(5 citation statements)

References 31 publications

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“…The leakage current improvement of the cell can be observed by Fig. 4, which shows only 20% leakage power as compared to that of the ST cell [3] array at 300 mV at room temperature. But the cell is still limited b its slower write speed.…”

Section: Sram Designmentioning

confidence: 91%

“…Stability has long been a major concern for SRAM. Low voltage operation and increased process variation caused by Random Dopant Fluctuation (RDF) & Line Edge Roughness (LER) have been shown to degrade the stability and performance of SRAM, and may lead to functional failure [3]. Aggressive power reduction can be achieved by subthreshold operation; however, operation at these reduced voltages degrades robustness, due to depleted noise margins and higher susceptibility to process variations and device mismatch.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity

Vishvakarma

Reniwal

Khuswah

et al. 2015

2015 IEEE International Symposium on Nanoelectronic and Information Systems

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The importance of embedded memory in contemporary multi-core processors and system-on-chip (SoC) for wearable electronics and IoT applications is growing. Intensive data processing in such processors and SoCs necessitates larger on-chip, energy-efficient static random access memory (SRAM). However, there are several challenges associated with low-voltage SRAMs. In this paper we have discussed the major hurdles at technology front for low power and robust SRAM design. We have discussed the different circuit techniques to mitigate these severe reliability concerns for embedded SRAM. Furthermore, this paper presented the recent development in embedded memory technology targeted to efficient computation. We have analyzed the effect of various device sizing on memory stability. The novel current mode circuit is also presented for high speed, offset tolerant SRAM sense amplifier. The FinFET memory design is explored to reduce the external manifestation of device mismatch on SRAM stability and memory yield.Keywords-Current Latch Sense Amplifier, Offset, SRAM, inter die variations, intra die variations.

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Section: Sram Designmentioning

confidence: 91%

Section: Introductionmentioning

confidence: 99%

Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity

Vishvakarma

Reniwal

Khuswah

et al. 2015

2015 IEEE International Symposium on Nanoelectronic and Information Systems

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show abstract

“…As the technology node of the MOS devices shifted into the nanometer region, it generates statistical quality deviations in transistor metrics including threshold voltage, channel length, and mobility [31]. Deviation in channel length leads to a change in threshold voltage which is a big challenge in nanoscale technology.…”

Section: Process Variationmentioning

confidence: 99%

A Low Leakage 9T SRAM Cell With Improve Stability in Sub-Threshold Region for IoT Applications

Kumar¹,

Tomar²

2021

Preprint

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This paper presents a single-ended read and differential write half select free 9T static random access memory (SRAM) cell operates in the sub-threshold region. Proposed 9T SRAM cell shows a reasonable reduction in read and write power dissipation by a factor of 1.41× and 2.1× respectively as of conventional 6T (Conv.6T) SRAM cell. The stacking of transistors at core latch network minimizes the leakage power of the cell. The read static noise margin (RSNM) and write margin (WM) are upgraded by 2.16× and 2.06× respectively as of Conv.6T cell. A forward body bias technique is utilized in read path which results to decreases in read access time by a factor of 2.72× as of standard 6T SRAM cell. The mean value of Ion/Ioff ratio of the proposed cell is improved by 2.92× as compared to the Conv.6T SRAM cell. It is attributed to a reduction in bit-line leakage current. To achieve more soundness in characteristics of the proposed 9T SRAM cell, process variation effect on RSNM, power dissipation, and read current is calculated through Monte Carlo (MC) simulation at 5000 points. The obtained results are compared with reference SRAM cells at 0.3V supply voltage.

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“…This HBW is helpful in preventing the negative capacitance turn into the positive capacitance as the gain A VN decreases with frequency. Moreover, in this topology, a right half plane pole or oscillation can occur only if the total gate capacitance of LDO become negative [7]. To keep the total gate capacitance from turning negative and causing instability, the small value of C FB or A VN can be designed to satisfy the condition C FB ð1 À A VN Þ !…”

Section: Proposed Ldo With Negative Capacitancementioning

confidence: 99%

LDO regulator with high power supply rejection at 10 MHz

Javed

Roh

2016

IEICE Electron. Express

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Statistical SRAM Read Access Yield Improvement Using Negative Capacitance Circuits

Cited by 10 publications

References 31 publications

Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity

Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity

A Low Leakage 9T SRAM Cell With Improve Stability in Sub-Threshold Region for IoT Applications

LDO regulator with high power supply rejection at 10 MHz

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