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Tunnel field effect transistor (TFET) is being considered as an alternative to the conventional MOSFETs for low power system on chip applications. In this Letter, gate-drain underlap (UL) feature of double gate TFET for analogue/RF characteristic is discussed. Here, it is found that parasitic resistance induced by gate drain UL is not significant as compared with DG tunnel field effect transistor (DG-FET). Thus, the behaviour of RF figure of merit is different from DG-FET.

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The tunnel field effect transistor (TFET) and its analog/RF performance is being aggressively studied at device architecture level for low power SoC design. Therefore, in this paper we have investigated the influence of the gate-drain underlap (UL) and different dielectric materials for the spacer and gate oxide on DG-TFET (double gate TFET) and its analog/RF performance for low power applications. Here, it is found that the drive current behavior in DG-TFET with a UL feature while implementing dielectric material for the spacer is different in comparison to that of DG-FET. Further, hetero gate dielectric-based DG-TFET (HGDG-TFET) is more resistive against drain-induced barrier lowering (DIBL) as compared to DG-TFET with high-k (HK) gate dielectric. Along with that, as compared to DG-FET, this paper also analyses the attributes of UL and dielectric material on analog/RF performance of DG-TFET in terms of transconductance (g m ), transconductance generation factor (TGF), capacitance, intrinsic resistance (Rdcr), cut-off frequency (F T ), and maximum oscillation frequency (F max ). The LK spacer-based HGDG-TFET with a gate-drain UL has the potential to improve the RF performance of device.