Analogue/RF performance attributes of underlap tunnel field effect transistor for low power applications

Vijayvargiya, Vikas; Reniwal, Bhupendra Singh; Singh, Pooran; Vishvakarma, Santosh Kumar

doi:10.1049/el.2015.3797

Cited by 21 publications

(17 citation statements)

References 6 publications

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“…TFET can be regarded as a promising alternative device of metal-oxide-semiconductors field effect transistor (MOSFET) to overcome the imperfection of short channel effects and betterment the characteristics of the device such as high ION/IOFF ratio, low OFF-current state lower subthreshold slope and minimize the power consumption [8]- [11]. The operating mechanism of TFET is based on the band-to-band tunneling phenomenon, while in MOSFET, the operating mechanism is based on the thermionic emission technique [12]- [14]. Besides all these advantages, but TFET is still suffering from some problems and facing challenges like low ON-current state, ambipolar behavior (conduction of current when the gate bias is negative), and higher parasitic capacitances [15]- [18].…”

Section: Introductionmentioning

confidence: 99%

Characterization of silicon tunnel field effect transistor based on charge plasma

Abdul-kadir

Taha

2022

IJEECS

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The aim of the proposed paper is an analytical model and realization of the characteristics for tunnel field-effect transistor (TFET) based on charge plasma (CP). One of the most applications of the TFET device which operates based on CP technique is the biosensor. CP-TFET is to be used as an effective device to detect the uncharged molecules of the bio-sample solution. Charge plasma is one of some techniques that recently invited to induce charge carriers inside the devices. In this proposed paper we use a high work function in the source (ϕ=5.93 eV) to induce hole charges and we use a lower work function in drain (ϕ=3.90 eV) to induce electron charges. Many electrical characterizations in this paper are considered to study the performance of this device like a current drain (ID) versus voltage gate (Vgs), ION/IOFF ratio, threshold voltage (VT) transconductance (gm), and sub-threshold swing (SS). The signification of this paper comes into view enhancement the performance of the device. Results show that high dielectric (K=12), oxide thickness (Tox=1 nm), channel length (Lch=42 nm), and higher work function for the gate (ϕ=4.5 eV) tend to best charge plasma silicon tunnel field-effect transistor characterization.

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Section: Introductionmentioning

confidence: 99%

Characterization of silicon tunnel field effect transistor based on charge plasma

Abdul-kadir

Taha

2022

IJEECS

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“…The fabrication process of TFETs varies from that of Mosfets in terms of their source doping. Thus, the fabrication of NS-TFET is comparatively easier to implement with minimal deviation from the NS-FET fabrication process [19][20].…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis of Vertically Stacked Nanosheet Tunnel Field Effect Transistor with Ideal Subthreshold Swing

Jain

Sawhney

Kumar

et al. 2021

Silicon

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In this paper, a novel vertically stacked silicon Nanosheet Tunnel Field Effect Transistor (NS-TFET) device scaled to a gate length of 12nm with Contact poly pitch (CPP) of 48nm is simulated. NS-TFET device is investigated for its electrostatics characteristics using technology computer-aided design (TCAD) simulator. The inter-band tunneling mechanism with a P-I-N layout has been incorporated in the stacked nanosheet devices. The asymmetric design technique for doping has been used for optimum results. NS-TFET provides a low leakage current of order10 -16 A, an excellent subthreshold swing (SW) of 23mv/decade, and negligible drain induced barrier lowering (DIBL) having a value of 10.5 mv/V. The notable ON to OFF current ratio of the order of 10 11 has been achieved. The device exhibits a high transconductance of 3.022x10 -5 S at the gate to source voltage of 1V. NS-TFET shows tremendous improvement in short channel effects (SCE) and is a good option for advanced technologies.

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“…Here, ballistic movement in TFET represents flow of charge carriers in a well‐mannered path without mutual scattering between them. Therefore, it exhibits the extraordinary properties of high immunity to SCEs, low leakage (OFF state) current, and low subthreshold swing [2–6].…”

Section: Introductionmentioning

confidence: 99%

Analysis of trap‐assisted tunnelling in asymmetrical underlap 3D‐cylindrical GAA‐TFET based on hetero‐spacer engineering for improved device reliability

Beohar

Yadav

Vishvakarma

2017

Micro & Nano Letters

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A unique design for an asymmetrical underlap (AU) cylindrical-gate-all-around (GAA)-n-tunnel field effect transistor (TFET) based on heterospacer engineering with trap-assisted tunnelling (TAT) for reliability concern is proposed and validated. Here, DC and analogue performances such as I ON , I OFF , SS, I ON /I OFF, C gs , and C gd have been investigated, while included TAT model and compared the examined device with AU GAA-TFET based on homo-spacer (HS) dielectric. On the basis of observation, the proposed device increases ON current as high as 2.1 × 10 −6 A/µm, which corresponds to 1024 times improvement in I ON /I OFF when compared with device based on HS. It also suppresses ambipolar behaviour with fast switching ON-OFF transition due to low leakage current (I OFF). These performances are mainly produced due to AU and low-k spacer dielectric which is replaced by high-k dielectric over source side spacer of the device, whereas drain side spacer is placed with high-k material along with increase in series resistance across drain-channel junction caused by drain underlap. Low-k spacer reduces the fringing field, and the depletion does not form at the source-gate edge, hence high source-channel tunnelling junction.

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Analogue/RF performance attributes of underlap tunnel field effect transistor for low power applications

Cited by 21 publications

References 6 publications

Characterization of silicon tunnel field effect transistor based on charge plasma

Characterization of silicon tunnel field effect transistor based on charge plasma

Performance Analysis of Vertically Stacked Nanosheet Tunnel Field Effect Transistor with Ideal Subthreshold Swing

Analysis of trap‐assisted tunnelling in asymmetrical underlap 3D‐cylindrical GAA‐TFET based on hetero‐spacer engineering for improved device reliability

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