Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design

Singh, Pooran; Reniwal, Bhupendra Singh; Vijayvargiya, Vikas

doi:10.1016/j.vlsi.2018.03.006

Cited by 20 publications

(25 citation statements)

References 28 publications

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“…The proposed D 2 LP10T cell is efficient for the low power and energy, which is very productive for the requirement of the LiFi application. 23 ; B, PFC10T 12 ; C, PPN10T 24 ; D, PNN10T 25 ; E, ST2 26…”

Section: Proposed D Lp10t Sram Cellmentioning

confidence: 99%

“…Moreover, the 6T cell also has the problem of half select issue, read/write conflict of stored data in storage node voltage. 6,7 To resolve all conditions, various design strategies have been suggested in the form of art circuits in the literature, such as read decoupling technique to isolate the read path from the storage node, 8,9 feedback cutting approach is used in the cross-coupled inverter to enhance the stability, [10][11][12] single-ended approach is used to enhance the read stability to a great extent, 13,14 stacking effect is used in the cross-coupled inverter or in the access path to reduce the leakage power dissipation, 15,16 write assist circuitry is used to reduce the write power and enhance the write stability, 17,18 half-select disturb-free strategy is used in an array to resolve the half select issue, 11,17 and the FinFET is also used as an alternative device to conventional planar-bulk MOSFET to reduce the V th variation. 19,20 The researchers have also worked in the subthreshold region with greater stability and robust architecture.…”

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confidence: 99%

“…14 But, there is limitation due to the higher delay and poor ability in the write operation. Now, for enhancing low power and high stability, positive feedback controlled (PFC) 10T SRAM cell 12 is designed. But the statistical distribution of RSNM in this cell is degraded and leakage power is increased due to high-temperature conditions.…”

mentioning

confidence: 99%

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An energy‐efficient data‐dependent low‐power 10T SRAM cell design for LiFi enabled smart street lighting system application

Gupta

Sharma²,

Shah

et al. 2020

Int J Numerical Modelling

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The LiFi enabled smart street lighting system requires the adaptive SoC to save huge amount of power/energy for data storage, which plays an important role for any urban area development. For the above application, an energy-efficient data-dependent power supplied 10T SRAM cell with half-select free readdecoupled circuit is designed to boost stability while stacking effect controls the leakage current against the process-voltage-temperature variations. CMOS 65 nm technology node is used for the implementation and comparison of various SRAM cells. The proposed cell offers 4×, 1.15×, and 1.66× higher read, hold, and write stability, respectively, as compared with the 6T cell at 0.4 V supply voltage. The improvement of write, read, and leakage power of the proposed 10T cell are 98.03%, 56.25%, and 91.07%, respectively, as compared with the 6T cell at 0.2 V supply. It is also observed that the proposed 10T cell has 88.88% and 85.71% write 0 and write 1 energy, respectively, as compared with the 6T cell at 0.2 V supply voltage. To better assess the cell, we introduced the figure of merit (FOM) and observed that the FOM of the proposed cell is 125× higher as compared with the 6T cell at 0.4 V supply voltage.

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Section: Proposed D Lp10t Sram Cellmentioning

confidence: 99%

mentioning

confidence: 99%

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An energy‐efficient data‐dependent low‐power 10T SRAM cell design for LiFi enabled smart street lighting system application

Gupta

Sharma²,

Shah

et al. 2020

Int J Numerical Modelling

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show abstract

“…The proposed SRAM cell is adopted to design a look up table for 6-inputs of FPGA and a 2kb SRAM macroblock. They achieved superior results in terms of write and read static noise margins; and less leakage power dissipation [10]. Y. Wang, et al proposed hypotheses for the underlying causes and validate power variations in processors based upon specifically governed environmental factors.…”

Section: Introductionmentioning

confidence: 99%

Multi-objective Pareto front and particle swarm optimization algorithms for power dissipation reduction in microprocessors

Sulaiman¹

2020

IJECE

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The progress of microelectronics making possible higher integration densities, and a considerable development of on-board systems are currently undergoing, this growth comes up against a limiting factor of power dissipation. Higher power dissipation will cause an immediate spread of generated heat which causes thermal problems. Consequently, the system's total consumed energy will increase as the system temperature increase. High temperatures in microprocessors and large thermal energy of computer systems produce huge problems of system confidence, performance, and cooling expenses. Power consumed by processors are mainly due to the increase in number of cores and the clock frequency, which is dissipated in the form of heat and causes thermal challenges for chip designers. As the microprocessor’s performance has increased remarkably in Nano-meter technology, power dissipation is becoming non-negligible. To solve this problem, this article addresses power dissipation reduction issues for high performance processors using multi-objective Pareto front (PF), and particle swarm optimization (PSO) algorithms to achieve power dissipation as a prior computation that reduces the real delay of a target microprocessor unit. Simulation is verified the conceptual fundamentals and optimization of joint body and supply voltages (Vth-VDD) which showing satisfactory findings.

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“…5 During the process of attempting to improve transistor performance, the double-gated transistors showed good potential towards improving the switching strength and hence the performance of the transistor. [6][7][8][9][10][11] Despite this improvement, the new structure introduced different types of dimensional variability. Thus, process variation continued to be one of the main challenges for design reliability.…”

Section: Introductionmentioning

confidence: 99%

System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation

Majzoub¹,

Taouil²,

Hamdioui³

2019

Journal of Low Power Electronics

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Standard low power design utilizes a variety of approaches for supply and threshold control to reduce dynamic and idle power. At a very early stage of the design cycle, the V dd and V th values are estimated, based on the power budget, and then used to scale the delay and estimate the design performance. Furthermore, process variation in sub-20 nm feature technologies introduces a substantial impact on speed and power. Thus, the impact of such variation on the scaled delay has to also be considered in the performance estimation. In this paper, we propose a system-level model to estimate this delay, taking into consideration voltage scaling under within-die process variation for both planar and FinFET CMOS transistors in the sub-20 nm regime. The model is simple, has acceptable accuracy and is particularly useful for architectural-level simulations for lowpower design exploration at an early stage in the design space exploration. The proposed model estimates the delay in different supply voltage and threshold voltage ranges. The model uses a modified alpha-power equation to measure the delay of the critical path of a computational logic core. The targeted technology nodes are 14 nm, 10 nm, and 7 nm for FinFETs, and 22 nm, and 16 nm for planar CMOS. Within-die process variation is assumed to be lumped in with the threshold voltage and the transistor channel length and width to simplify its impact on delay. For the given technology nodes, the average percentage error numbers of theproposed delay equation compared to hSpice are between 0.5% to 14%.

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Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design

Cited by 20 publications

References 28 publications

An energy‐efficient data‐dependent low‐power 10T SRAM cell design for LiFi enabled smart street lighting system application

An energy‐efficient data‐dependent low‐power 10T SRAM cell design for LiFi enabled smart street lighting system application

Multi-objective Pareto front and particle swarm optimization algorithms for power dissipation reduction in microprocessors

System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation

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