Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity

Abstract

The importance of embedded memory in contemporary multi-core processors and system-on-chip (SoC) for wearable electronics and IoT applications is growing. Intensive data processing in such processors and SoCs necessitates larger on-chip, energy-efficient static random access memory (SRAM). However, there are several challenges associated with low-voltage SRAMs. In this paper we have discussed the major hurdles at technology front for low power and robust SRAM design. We have discussed the different circuit techniques to mitigate these severe reliability concerns for embedded SRAM. Furthermore, this paper presented the recent development in embedded memory technology targeted to efficient computation. We have analyzed the effect of various device sizing on memory stability. The novel current mode circuit is also presented for high speed, offset tolerant SRAM sense amplifier. The FinFET memory design is explored to reduce the external manifestation of device mismatch on SRAM stability and memory yield.Keywords-Current Latch Sense Amplifier, Offset, SRAM, inter die variations, intra die variations.

6T CMOS SRAM Stability in Nanoelectronic Era: From Metrics to Built-in Monitoring

“…As larger densities of static memories are embedded inside complex SoC designs, analyzing memory reliability becomes more critical, as it may be an important source of the overall system error rate. For instance, the contribution of the SRAM parameter variability dominates the overall circuit parameter characteristics, including leakage and yield [1]. In addition, a deep knowledge and analysis about the SRAM cell noise margin and the impact of physical parameters variation is therefore becoming a must in modern CMOS designs.…”