LDO regulator with high power supply rejection at 10 MHz

Abstract

A new high-frequency power supply rejection (PSR) improvement technique is presented for a low-dropout (LDO) regulator. The proposed technique utilizes a negative capacitance at the gate of the power transistor to enhance the PSR at high frequencies by neutralizing the effect of parasitic capacitances. The simulation results show that the LDO is able to achieve a PSR of −67.9 dB at 10 MHz.

A fast-transient dual loop LDO with high PSR

“…Many excellent designs of LDOs with high PSR and fast-transient response have reported in literature, such as a fast-transient response LDO with 67.9 dB of PSR at 10 MHz in [7]. However, many of them [7][8][9][10][11][12] needs μF−level off-chip capacitor for stability, PSR enhancement and transient improvement, which may be not good solutions in SoC.…”

“…Many excellent designs of LDOs with high PSR and fast-transient response have reported in literature, such as a fast-transient response LDO with 67.9 dB of PSR at 10 MHz in [7]. However, many of them [7][8][9][10][11][12] needs μF−level off-chip capacitor for stability, PSR enhancement and transient improvement, which may be not good solutions in SoC. Capacitor-less LDOs are the preferred architecture solution as they can be fully integrated, and as a result, bill of material and printed circuit board (PCB) area are reduced [13,14].…”