No abstract

We investigate the time-dependent shift in the threshold voltage of amorphous silicon thin-film transistor stressed with constant drain current. We observe a nonsaturating power-law time dependence, which is in contrast to the conventional stretched exponential that saturates at prolonged stress time. The result is consistent with the carrier-induced defect creation model and corroborates the nonlinear dependence of the rate of defect creation on the band-tail carrier density.

No abstract

Scaling transistor size to the scale of the nanometer coupled with reduction of supply voltage has made SRAMs more vulnerable to soft errors than ever before. The vulnerability has been accentuated by increased variability in device parameters. In this paper, we present an analytical model for critical charge in order to assess the soft error vulnerability of 6T SRAM cell. The model takes into account the dynamic behavior of the cell and demonstrates a simple technique to decouple the nonlinearly coupled storage nodes. Decoupling of storage nodes enables solving associated current equations to determine the critical charge for an exponential noise current. The critical charge model thus developed consists of both NMOS and PMOS transistor parameters. Consequently, the model can estimate critical charge variations due to variability of transistor parameters and manufacturing defects, such as resistive contacts and vias. In addition, the model can serve as a tool to optimize the hibernation voltage of low-power SRAMs or the size of MIM capacitor per cell in order to achieve a target soft error robustness. Critical charge calculated by the model is in good agreement with SPICE simulations for a commercial 90-nm CMOS process with a maximum discrepancy of less than 5%.Index Terms-Critical charge, process-induced variability, soft error, SRAM.

No abstract