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Test chips built in a 32nm bulk CMOS technology consisting of hardened and non-hardened sequential elements have been exposed to neutrons, protons, alpha-particles and heavy ions. The radiation robustness of two types of circuit-level soft error mitigation techniques has been tested: 1) SEUT (Single Event Upset Tolerant), an interlocked, redundant state technique, and 2) a novel hardening technique referred to as RCC (Reinforcing Charge Collection). This work summarizes the measured soft error rate benefits and design tradeoffs involved in the implemented hardening techniques.