Comparison of alpha-particle and neutron-induced combinational and sequential logic error rates at the 32nm technology node

Gill, B.; Seifert, N.; Zia, V.

doi:10.1109/irps.2009.5173251

Cited by 90 publications

(53 citation statements)

References 26 publications

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“…In this regard, however, it has been proven [13,14] that SEUs affecting storage elements (latches and flip-flops) within sequential logic are by far the largest contributor to soft error rate (SER) in logic. For this reason, extensive research efforts have been recently devoted to devising novel hardening schemes/approaches for latches and flips-flops.…”

Section: Introductionmentioning

confidence: 99%

High-Performance Robust Latches

Omaña

Rossi

Metra

2010

IEEE Trans. Comput.

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obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The WestminsterResearch online digital archive at the University of Westminster aims to make the research output of the University available to a wider audience. Copyright and Moral Rights remain with the authors and/or copyright owners.Whilst further distribution of specific materials from within this archive is forbidden, you may freely distribute the URL of WestminsterResearch: ((http://westminsterresearch.wmin.ac.uk/). Abstract-First a new high performance robust latch (referred to as HiPeR latch) is presented, that is insensitive to transient faults affecting its internal and output nodes by design, independently of the size of its transistors. Then, a modified version of the HiPeR latch (referred as HiPeR-CG) is proposed, that is suitable to be used together with clock gating. Both proposed latches are faster than the latches most recently presented in the literature, while providing better or comparable robustness to transient faults, at comparable or lower costs in terms of area and power, respectively. Therefore, thanks to the good tradeoffs in terms of performance, robustness and cost, our proposed latches are particularly suitable to be adopted on critical paths.

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Section: Introductionmentioning

confidence: 99%

High-Performance Robust Latches

Omaña

Rossi

Metra

2010

IEEE Trans. Comput.

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“…We use parallelized inverter chains as a target circuit and bundle them to a single pulse-width measurement circuit. Similar parallelization is found in [4]. Using this structure, while we can suppress the pulse-width modulation by using short inverter chains, we can increase the area ratio of the target circuit to the measurement circuit.…”

Section: Introductionmentioning

confidence: 64%

SET pulse-width measurement eliminating pulse-width modulation and within-die process variation effects

Harada

Mitsuyama

Hashimoto

et al. 2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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Abstract-This paper presents a measurement circuit structure for capturing SET pulse-width suppressing pulse-width modulation and within-die process variation effects. For mitigating pulse-width modulation while maintaining area efficiency, the proposed circuit uses massively parallelized short inverter chains as a target circuit. Moreover, for each inverter chain on each die, pulse-width calibration is performed. In measurements, narrow SET pulses ranging 5 ps to 215 ps were obtained. We confirm that an overestimation of pulse-width may happen when ignoring die-to-die and within-die variation of the measurement circuit. Our evaluation results thus point out that calibration for within-die variation in addition to die-to-die variation of the measurement circuit is indispensable.

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“…Indeed, [18] reports the alpha-particle soft error rate (SER) measured increases of ≈2-3x when reducing voltage from 0.95V to 0.75V in a 32nm circuit, while [4] reports a doubling in SER when reducing voltage from 0.7V to 0.5V in 28nm. Furthermore, the rate of propagation of a glitch through the circuit is dependent on the linear energy transfer (LET) of the particle strike.…”

Section: Motivationmentioning

confidence: 99%

Dynamic transient fault detection and recovery for embedded processor datapaths

Bournoutian

Orailoğlu

2012

Proceedings of the Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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As microprocessors continue to evolve and grow in functionality, the use of smaller nanometer technology scaling coupled with high clock frequencies and exponentially increasing transistor counts dramatically increases the susceptibility of transient faults. However, the correct and reliable operation of these processors is often compulsory, both in terms of consumer experience and for high-risk embedded domains such as medical and transportation systems. Thus, economical fault detection and recovery becomes essential to meet all necessary market requirements. This paper explores the efficient leveraging of superscalar, out-of-order architectures to enable multi-cycle transient fault-tolerance throughout the datapath in a novel manner. By using dynamic instruction execution redundancy, soft errors within the datapath are both detected and recovered. The proposed microarchitecture selectively reevaluates corrupted instructions, reducing the recovery impact by preserving completed instructions unaffected by the fault. The additional computational workload is dynamically staggered to leverage the out-of-order nature of the architecture and minimize resource conflicts and delays.

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Comparison of alpha-particle and neutron-induced combinational and sequential logic error rates at the 32nm technology node

Cited by 90 publications

References 26 publications

High-Performance Robust Latches

High-Performance Robust Latches

SET pulse-width measurement eliminating pulse-width modulation and within-die process variation effects

Dynamic transient fault detection and recovery for embedded processor datapaths

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