SET pulse-width measurement eliminating pulse-width modulation and within-die process variation effects

This paper presents a measurement circuit structure for capturing SET pulse-width suppressing pulse-width modulation and within-die process variation effects. For mitigating pulse-width modulation while maintaining area efficiency, the proposed circuit uses massively parallelized short inverter chains as a target circuit. Moreover, for each inverter chain on each die, pulse-width calibration is performed. In measurements, narrow SET pulses ranging 5 ps to 215 ps were obtained. We confirm that an overestimation of pulse-width may happen when ignoring die-to-die and within-die variation of the measurement circuit. Our evaluation results thus point out that calibration for within-die variation in addition to die-to-die variation of the measurement circuit is indispensable. key words: soft error, single event transient (SET), pulse-width, pulsewidth modulation, measurement circuit, within-die process variation Ryo Harada (S'09) received the B.E. and M.E. degrees in Information Systems Engineering from Osaka University, Osaka, Japan, in 2009. He is currently pursuing the Ph.D. degree in the Department of Information Systems Engineering at Osaka University. His research interests include soft error estiomation. Yukio Mitsuyama received B.E., M.E., and Ph.D. degrees in Information Systems Engineering from Osaka University, Japan, in 1998, 2000, and 2010, respectively. He is currently an Associate Professor in School of Engineering, Kochi University of Technology. His research interests include reconfigurable architecture and its VLSI design. He is a member of IEEE and IPSJ. sity. His research interest includes computeraided design for digital integrated circuits, and high speed and low power circuit design. Dr. Hashimoto served on the technical program committees for international conferences including DAC, ICCAD, ITC, Symposium on VLSI Circuits, ASP-DAC, DATE, and ISPD. He is a member of IEEE, ACM and IPSJ. Takao Onoye received the B.E. and M.E. degrees in Electronic Engineering, and Dr.Eng. degree in Information Systems Engineering all from Osaka University, Japan, in 1991Japan, in , 1993Japan, in , and 1997. He is currently a professor in the Department of Information Systems Engineering, Osaka University. His research interests include media-centric low-power architecture and its SoC implementation. He is a member of IEEE, IPSJ, and ITE-J.

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“…† Similar parallelization for SET pulse-width measurement is reported in[5], but a preliminary work of this paper[6] was published before[5].…”

mentioning

confidence: 76%

SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects

Harada

Mitsuyama

Hashimoto

et al. 2014

IEICE Trans. Fundamentals

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“…Typically, SET pulse widths are measured by a logic gate chain and a time-to-digital converter (TDC) such as vernier delay line [19], [20]. When a SET pulse is generated by radiation passing through one logic gate, the SET propagates through the logic gate chain and is input to the TDC.…”

Section: Conventional Measurement Structuresmentioning

confidence: 99%

Measuring SET Pulse Widths in pMOSFETs and nMOSFETs Separately by Heavy Ion and Neutron Irradiation

FURUTA,

SUGITANI,

NAKAJIMA

et al. 2024

IEICE Trans. Electron.

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Radiation-induced temporal errors become a significant issue for circuit reliability. We measured the pulse widths of radiationinduced single event transients (SETs) from pMOSFETs and nMOSFETs separately. Test results show that heavy-ion induced SET rates of nMOS-FETs were twice as high as those of pMOSFETs and that neutron-induced SETs occurred only in nMOSFETs. It was confirmed that the SET distribution from inverter chains can be estimated using the SET distribution from pMOSFETs and nMOSFETs by considering the difference in load capacitance of the measurement circuits.

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Characterization of Heavy Ion Induced SET Features in 22-nm FD-SOI Testing Circuits

Cai

Liu

et al. 2020

IEEE Access

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With device scaling-down, circuits appear more susceptible to transient faults especially for the bulk silicon process. Thus, FD-SOI technology has been widely popular in serious radiation environment due to its high radiation-tolerance inherence created by an additional BOX layer. In this work, seven different inverter chains with two kinds of core voltages, four kinds of channel areas and a stack inverter chain are designed to investigate the SET in advanced 22 nm FD-SOI CMOS technology. A NAND chain is also designed and used for comparison with inverter chains. The sensitivities of diverse SET targets are characterized with different core voltages and heavy-ion tilts. Results showed that the inverter size and the driving current can dominate the occurrence and width distribution of transient pulses. Besides, heavy-ion strike angle, LET, and charge sharing can also affect the pulse width. Though a high LET can deposit adequate energy, the widest pulses are measured in low-LET 84 Kr ion irradiation, rather than in high-LET ions' irradiation, which are attributed to the pulse quenching effect and being investigated by Hspice simulation. The LET dependency and low voltage induced SET widening are all observed in irradiation tests and verified by circuit-level pulse injection. All of the SET sensitive targets are distinguished. The results are highly effective for the designers to suppress and correct the SET-oriented errors to achieve a radiation robust system. INDEX TERMS Fully-depleted silicon-on-insulator (FD-SOI), heavy ions, inverter, single event transient.

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SET pulse-width measurement eliminating pulse-width modulation and within-die process variation effects

Cited by 6 publications

References 13 publications

SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects

SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects

Measuring SET Pulse Widths in pMOSFETs and nMOSFETs Separately by Heavy Ion and Neutron Irradiation

Characterization of Heavy Ion Induced SET Features in 22-nm FD-SOI Testing Circuits

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