2005
DOI: 10.1063/1.1993766
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Threshold voltage instability of amorphous silicon thin-film transistors under constant current stress

Abstract: We investigate the time-dependent shift in the threshold voltage of amorphous silicon thin-film transistor stressed with constant drain current. We observe a nonsaturating power-law time dependence, which is in contrast to the conventional stretched exponential that saturates at prolonged stress time. The result is consistent with the carrier-induced defect creation model and corroborates the nonlinear dependence of the rate of defect creation on the band-tail carrier density.

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Cited by 75 publications
(63 citation statements)
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“…1, 3͑c͒, and 4͔ and explained by the fact that highly crystalline CLC poly-Si has a few densities of tail states to accommodate accumulated carriers, inhibiting markedly deep-state generation in channel layers by bias stressing. 20,21 Under gate-bias stressing ͑or HCS with no drain bias͒, in thicker channels with greater channel crystallinity, the carrier-trapping effect is weaker because grain defects are fewer and so the change in V t is smaller and larger exponents are associated with the ⌬V th , as observed in currently used devices ͓Figs. 3͑c͒ and 4͔.…”
mentioning
confidence: 96%
“…1, 3͑c͒, and 4͔ and explained by the fact that highly crystalline CLC poly-Si has a few densities of tail states to accommodate accumulated carriers, inhibiting markedly deep-state generation in channel layers by bias stressing. 20,21 Under gate-bias stressing ͑or HCS with no drain bias͒, in thicker channels with greater channel crystallinity, the carrier-trapping effect is weaker because grain defects are fewer and so the change in V t is smaller and larger exponents are associated with the ⌬V th , as observed in currently used devices ͓Figs. 3͑c͒ and 4͔.…”
mentioning
confidence: 96%
“…In particular, the positive shift of the threshold voltage (V th ) leads to a reduction in the luminance and causes image problems in OLEDs. 24,[27][28][29][30] Thus, a highly stable material is desirable. Using the concept of a vacancy suppressor in amorphous films, further intentional doping of the base oxide with metals has been demonstrated.…”
mentioning
confidence: 99%
“…Another aspect that is worth mentioning is that most of the final DV T is verified after the first 24 h of stress and the data do not show a trend to a continuous increase in this value with time, so it might be expected that even with longer stress times the obtained DV T should not be very different from the 0.69 V obtained here. It is also interesting to compare these values with the ones typically found in the literature for a-Si:H TFTs: DV T exceeding 6 V (one order of magnitude higher) is obtained under the same testing procedure in [100], which is a good indication of the excellent stability of amorphous oxide semiconductors. Figure 6.35 shows some prototypes of a-GIZO matrices produced in our laboratory, while Figure 6.36 shows a working display with a resolution of 128 Â 128 pixels.…”
Section: Tft Stability Under Constant Current Stressmentioning
confidence: 67%