An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs

Abstract

Scaling transistor size to the scale of the nanometer coupled with reduction of supply voltage has made SRAMs more vulnerable to soft errors than ever before. The vulnerability has been accentuated by increased variability in device parameters. In this paper, we present an analytical model for critical charge in order to assess the soft error vulnerability of 6T SRAM cell. The model takes into account the dynamic behavior of the cell and demonstrates a simple technique to decouple the nonlinearly coupled storage nodes. Decoupling of storage nodes enables solving associated current equations to determine the critical charge for an exponential noise current. The critical charge model thus developed consists of both NMOS and PMOS transistor parameters. Consequently, the model can estimate critical charge variations due to variability of transistor parameters and manufacturing defects, such as resistive contacts and vias. In addition, the model can serve as a tool to optimize the hibernation voltage of low-power SRAMs or the size of MIM capacitor per cell in order to achieve a target soft error robustness. Critical charge calculated by the model is in good agreement with SPICE simulations for a commercial 90-nm CMOS process with a maximum discrepancy of less than 5%.Index Terms-Critical charge, process-induced variability, soft error, SRAM.

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“…The circuit simulation setup for critical charge evaluation is found in [1]. We used a simple current pulse model similarly to [24]. Therefore, He and heavier ions are the dominant secondary ions causing SEUs in 0.4-V operation because these ions occupy 89% of the SEU probability at 1.4 fC of critical charge.…”

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“…Conventionally, the current pulse is expressed as [21], (1) where is the total collected charge and is the rising (falling) time constant.…”

“…Fig. 2 shows the critical charge of the 10T memory cell used to evaluate SER (see Section III) as a function of the supply voltage, when and in (1) were set to 1 and 50 ps, respectively, in accordance with the model of Jahinuzzaman et al [21]. In our design, PMOSs (M3 and M4 in Fig.…”

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