A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability

This paper presents an improved design of a radiationhardened static random access memory (SRAM). The simulation results based on the 0.18 μm standard digital CMOS technology show that its static current drops dramatically compared with the WHIT cell, and the write speed is equivalent to that of other cells. The memory cell is extremely tolerant to logic upset as it does not flip even for a transient pulse with 100 times the critical charge of the ROCK cell. According to these features, this novel cell suits high reliability applications, such as aerospace and military.

Section: Simulation Results and Evaluationmentioning

confidence: 99%

“…1 (c)) [5]. Recently, a quad-node ten transistor (10T) SRAM cell has been proposed by Jahinuzzaman [6]. This cell offers differential read operation for easier design of the sense amplifier and reliable sense operation under the worst case conditions.…”

Section: Introductionmentioning

confidence: 99%

A novel single event upset hardened CMOS SRAM cell

Zhang

Shao

Liang

et al. 2012

“…For Quatro-10T as well as DICE cells, one does not constantly demonstrate superior hardening performance over the other [9]. Nevertheless, as an alternative to DICE, Quatro-10T has been shown to be more powerful and area efficient [4]. On the other hand, it displays larger noise margin in sub-0.4V regime with less leakage current than DICE cell.…”

Section: Introductionmentioning

confidence: 99%

“…Moreover, with technology scaling, circuit nodal capacitances and supply voltage has been reduced radically, which makes static random access memory (SRAM) more vulnerable to SEU. For SEU tolerable design, two types of hardened cell Quatro-10T [4] and DICE [5], as memory or latch or flip-flop cell, are broadly studied owing to their good SEU immunes [4,5,6,7,8]. DICE majorly relies on the extra principle of dual node feedback control to make it fully immune against a single node upset.…”

Section: Introductionmentioning

confidence: 99%

A radiation harden enhanced Quatro (RHEQ) SRAM cell

Peng

Chen

Zhang

et al. 2017

This paper intends to present a novel radiation-hardened SRAM cell by using the PMOS transistors stacked (each PMOS is split into two same sizes) and changing the inner topological structure on basis of the Quatro-10T. Combined with layout-level optimization design, the 3-D TCAD mixed-mode simulation results show that the novel design has a great single event upset (SEU) immune. Simultaneously, it is found to be tolerant of partial single-event multiple-node upsets (SEMNUs) due to the charge sharing among off-PMOS transistors. In addition, compared with the Quatro-10T, our proposed structure exhibits larger static noise margin (SNM) as well as lower power consumption in 65 nm COMS technology.

“…Once the data stored in the SRAM is changed, this might result in system failure. Thus, lots of approaches at different levels have been designed to harden the SRAM against SEU [2,3,4,5,6,7]. Of these hardening methods, single error correction (SEC) is an effective approach to mitigate the SEU in SRAM.…”

Section: Introductionmentioning

confidence: 99%

A novel layout placement structure to mitigate the multi-bit-upset in 6T-SRAM cell

Zeng

2014

A novel layout structure for the typical 6T-SRAM cell is designed to mitigate the single-event induced MBU. And three-dimensional technology computer-aided design (TCAD) numerical simulation is used to evaluate the MBU hardening performance of this novel layout structure. Compared to other layout structures, our proposed layout can effectively attenuate the single-event induced MBU in typical 6T-SRAM with little area and power penalty.