A novel single event upset hardened CMOS SRAM cell

Abstract

This paper presents an improved design of a radiationhardened static random access memory (SRAM). The simulation results based on the 0.18 μm standard digital CMOS technology show that its static current drops dramatically compared with the WHIT cell, and the write speed is equivalent to that of other cells. The memory cell is extremely tolerant to logic upset as it does not flip even for a transient pulse with 100 times the critical charge of the ROCK cell. According to these features, this novel cell suits high reliability applications, such as aerospace and military.

Assessing alpha-particle-induced SEU sensitivity of flip-chip bonded SRAM using high energy irradiation

“…SRAM is the most susceptible electronic device to the ionization radiation. To reduce its vulnerability against radiation, many radiationhardened and tolerant memory cells' designs have been proposed, like [2,3]. Advanced memory devices are packaged upside down to achieve high-density packaging and for heat dissipation mitigation.…”

A novel SEU hardened SRAM bit-cell design

“…To simulate the injection of a particle and its associated charge deposition, an incoming (for the drain of OFF-state PMOS storing "0") or outgoing (for the drain of OFF-state NMOS storing "1") double exponential current pulse is usually connected to the sensitive node in Cadence Spectre as described below [6] …”

“…In addition, some inner nodes of this cell are not robust enough and its critical charge is only 3 times that of the standard 6T cell [5]. A 18T cell [6] in Fig. 1(b) and a 14T cell [5] in Fig.…”

A novel SEU tolerant SRAM data cell design

“…These transistors operating on linear region create spatial redundancy of data. Additionally, transistors P5, P6, N5 and N6 are added to form the virtue of latch design as cell proposed in [7], which help storage nodes recover to their original value once the inner node is hit by SEU.…”