A novel SEU tolerant SRAM data cell design

Abstract

An improved SEU tolerant SRAM data cell design is presented here. The cell enhances the capability of SEU tolerance by creating spatial redundancy of data and virtue of latch design. The results show that our proposed design achieves high resilience to SEU and provides a 300 times increase in critical charge compared to standard 6T cell without much degradation in speed and Power dissipation. It shows that our design is very suitable for applying in high-reliability circuit and system design.

A novel SEU hardened SRAM bit-cell design

“…An extremely high critical charge is achieved, over 1000 times larger than that of the standard 6T cell, which ensures high reliability of the proposed cell in harsh radiation environments. Meanwhile, the Quatro-10T cell [5] 18T cell [6] 14T cell [5] Proposed cell proposed cell has comparable performances to previous SEU hardened designs, promising well-suited high performance applications.…”

“…For fair comparison, the 18T cell which is originally designed in 0.18 µm standard digital CMOS technology is also implemented in 65 nm bulk CMOS technology, so that all data cells are compared at 65 nm technology node. Simulations of the proposed cell and the 18T cell are carried out with Cadence Spectre tool and 65 nm bulk CMOS models at 1.2 V voltage supply at room temperature with the working frequency of 100 MHz, while data for other cells under identical simulation conditions are obtained from published literature [5,6]. The performance summary for comparative SEU hardened SRAM cells is shown in Table I.…”

“…1(a) was proposed for promising low voltage and low power applications, but researches have pointed out that this cell suffers from high write failure probability under process and temperature variations, impeding the application of this SRAM bit-cell [4]. In addition, some inner nodes of this cell are not robust enough and its critical charge is only 3 times that of the standard 6T cell [5]. A 18T cell [6] in Fig.…”

Design and verification of universal evaluation system for single event effect sensitivity measurement in very-large-scale integrated circuits

“…There existed problems such as rudimentary function and identification ways, low efficiency, low testing frequency and high costs in the specially designed SEE testing systems in the previous reports [4,7,14,17,18,19,20,21,22,23,24,25,26,27]. Other methods, such as a convenient test implemented by the commercial evaluation board have also been published [28].…”

Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications

“…On the other hand, the particle may directly strike an OFF-state transistor in a storage element, causing a single-node upset (SNU). Moreover, with the aggressive CMOS technology scaling, circuit integration is becoming much higher and node To mitigate SNUs or even DNUs, using radiation hardening by design (RHBD) techniques, many novel designs of latches [5][6][7] and flip-flops [8][9][10] are proposed, while the other designs mainly consider hardening for static random access memory (SRAM) cells [11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26]. This paper mainly considers hardening for SRAMs.…”