Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model

Jahinuzzaman, Shah M.; Sharifkhani, Mohammad; Sachdev, Manoj

doi:10.1109/isqed.2008.4479727

Cited by 16 publications

(17 citation statements)

References 10 publications

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“…The previous critical charge models, introduced in [19]- [22], exhibit some limitations, that make them incapable of modeling the WID variations. For example, the model introduced in [19] modeled as follows:…”

Section: Review Of the Previous Critical Charge Modelsmentioning

confidence: 99%

“…Finally, the work in [22] introduces a very accurate model in calculating . However, the value of the injected current pulse charge is obtained via iterative transient simulations by increasing by a small amount ( 0.001 fC) in SPICE till flipping occurs.…”

Section: Review Of the Previous Critical Charge Modelsmentioning

confidence: 99%

“…In [19]- [21], different models for the critical charge are proposed, however, these models overestimate the critical charge value and provide little insights to circuit designers. In [22], an analytical model to estimate the critical charge is presented. Despite its accuracy in modeling the critical charge, this model depends mainly on SPICE simulations.…”

Section: Introductionmentioning

confidence: 99%

“…Thus, this model can be used only when dealing with D2D variations. These D2D variations are estimated by applying corner-based analysis that have been already performed in [22]. These techniques tend to be inefficient, and completely pessimistic in the presence of relatively large variations.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A Design-Oriented Soft Error Rate Variation Model Accounting for Both Die-to-Die and Within-Die Variations in Submicrometer CMOS SRAM Cells

Mostafa

Anis

Elmasry

2010

IEEE Trans. Circuits Syst. I

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Submicrometer static random access memory cells are more susceptible to particle strike soft errors and increased statistical process variations, in advanced nanometer CMOS technologies. In this paper, analytical models for the critical charge variations accounting for both die-to-die and within-die variations are proposed. The derived models are verified and compared to Monte Carlo simulations by using industrial 65-nm CMOS technology. This paper provides new design insights such as the impact of the coupling capacitor, one of the most common soft error mitigation techniques, on the critical charge variability, especially, at lower supply voltages. It demonstrates that two extreme values of this coupling capacitor exist. The first value results in maximum relative variations and the other results in minimum relative variations. Therefore, the circuit designers can utilize these results to design the coupling capacitor to limit the variations under power and performance constraints in early design cycles. The derived analytical models account for the impact of the supply voltage and different particle strike conditions. These results are particularly important for soft error tolerant and variation tolerant designs in submicrometer technologies, especially, for low power operations.Index Terms-Deep submicrometer, process variations, reliability, soft errors, static random access memory (SRAM).

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Section: Review Of the Previous Critical Charge Modelsmentioning

confidence: 99%

Section: Review Of the Previous Critical Charge Modelsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Design-Oriented Soft Error Rate Variation Model Accounting for Both Die-to-Die and Within-Die Variations in Submicrometer CMOS SRAM Cells

Mostafa

Anis

Elmasry

2010

IEEE Trans. Circuits Syst. I

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“…Therefore, the dynamic stability analysis described in the following section is used to find the optimum pull up transistor sizing for both good write-ability and resilience to soft errors. [7]. Q crit is the minimum charge that needs to be deposited at the sensitive node of an SRAM cell to flip the stored bit.…”

Section: Static Noise Margin and Write-abilitymentioning

confidence: 99%

A Highly-Stable Nanometer Memory for Low-Power Design

Lin

Kim

Lombardi

2008

2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems

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A nine transistor (9T) cell at a 32nm feature size in CMOS is proposed to accomplish improvements in stability as well as power dissipation compared with previous designs for low-power memory operation. Initially, this paper shows that the proposed 9T SRAM cell can be used for robust, high-density design. Then, an optimum sizing is found for this 9T cell by considering stability, energy consumption, and performance. A write bitline balancing scheme is proposed to further reduce the power consumption of the SRAM cell. The impact of process variations is investigated in detail, and the power reduction of the 9T SRAM cell is verified under parameter variations.

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Impact of Soft Errors in a Jet Engine Controller

Hannius

Karlsson

2012

Lecture Notes in Computer Science

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Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model

Cited by 16 publications

References 10 publications

A Design-Oriented Soft Error Rate Variation Model Accounting for Both Die-to-Die and Within-Die Variations in Submicrometer CMOS SRAM Cells

A Design-Oriented Soft Error Rate Variation Model Accounting for Both Die-to-Die and Within-Die Variations in Submicrometer CMOS SRAM Cells

A Highly-Stable Nanometer Memory for Low-Power Design

Impact of Soft Errors in a Jet Engine Controller

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