A Highly-Stable Nanometer Memory for Low-Power Design

Lin, Sheng; Kim, Yong-Bin; Lombardi, Fabrizio

doi:10.1109/ndcs.2008.10

Cited by 23 publications

(11 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The conventional 6T SRAM cell and the cells in [7], [8], [32] use differential BLs for both Read and Write operations. The cells with single Read buffer in [9]- [23], [26]- [31] use differential Write BLs (WBL) for Write operation and single Read BL for Read operation. Fig.…”

Section: Single Bl For Bl Power Savingmentioning

confidence: 99%

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

Lin

Tsai

et al. 2012

IEEE J. Solid-State Circuits

156

View full text Add to dashboard Cite

This paper presents a novel single-ended disturb-free 9T subthreshold SRAM cell with cross-point data-aware Write word-line structure. The disturb-free feature facilitates bit-interleaving architecture, which can reduce multiple-bit upsets in a single word and enhance soft error immunity by employing Error Checking and Correction (ECC) technique. The proposed 9T SRAM cell is demonstrated by a 72 Kb SRAM macro with a Negative Bit-Line (NBL) Write-assist and an adaptive Read operation timing tracing circuit implemented in 65 nm low-leakage CMOS technology. Measured full Read and Write functionality is error free with V down to 0.35 V ( 0.15 V lower than the threshold voltage) with 229 KHz frequency and 4.05 µW power. Data is held down to 0.275 V with 2.29 µW Standby power. The minimum energy per operation is 4.5 pJ at 0.5 V. The 72 Kb SRAM macro has wide operation range from 1.2 V down to 0.35 V, with operating frequency of around 200 MHz for V around/above 1.0 V. Index Terms-Low power, low voltage, negative bit-line (BL), subthreshold SRAM cell, timing tracing.

show abstract

Section: Single Bl For Bl Power Savingmentioning

confidence: 99%

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

Lin

Tsai

et al. 2012

IEEE J. Solid-State Circuits

156

View full text Add to dashboard Cite

show abstract

“…Down-scaling of supply voltage is considered an effective method to reduce power consumption. Supply voltage scaling reduces dynamic power quadratically and leakage power exponentially [1]. However, the static noise margin (SNM), which reflects the cell stability, is degraded when the supply voltage is reduced.…”

Section: Introductionmentioning

confidence: 99%

A data-aware write-assist 10T SRAM cell with bit-interleaving capability

Mansore¹,

Gamad²

2018

Turk J Elec Eng & Comp Sci

View full text Add to dashboard Cite

Cell stability is becoming an important design concern as process technology continues to scale down. In this paper, we present a single-ended 10T SRAM cell that improves simultaneously both read static noise margin (RSNM) and write static noise margin (WSNM) by employing separate read buffer and power gating transistors, respectively. The cross-point write structure of the proposed cell facilitates bit-interleaved architecture to enhance soft-error immunity. Simulation is done on 65-nm CMOS technology on Cadence. Simulation results show that the RSNM of the proposed SRAM cell is 2.78 times and 1.47 times higher than those of the conventional 6T and Schmitt trigger-based 10T (ST-2) cells, respectively, at 0.4 V. The WSNM of the proposed design is 5.14 times larger than that of the two-port disturbfree 9T (TPDF9T) cell (without write assist) at 0.4 V. Write delay of the proposed cell is 77.56% less than that of the TPDF9T cell at 0.4 V. Leakage power dissipation of the proposed SRAM cell is 0.89 times that of the ST-2 cell at 0.4 V. The proposed cell occupies 1.34 times more area than the conventional 6T cell.

show abstract

“…Hence, by operating the cell in sub threshold region (i.e. by lowering the supply voltage below threshold voltage), it is made to achieve low power SRAM cell [11]- [14].…”

Section: Introductionmentioning

confidence: 99%

Design of 3T Gain Cell for Ultra Low Power Applications

Lavanya¹

2017

IJRASET

View full text Add to dashboard Cite

Design of a power efficient SRAM cell is one of the most important factor in order to achieve better chip performance. This paper presents a stable SRAM Gain Cell for low power applications. The 6T SRAM has been the traditional choice for the implementation of embedded memories due to its high-access speed and refresh-free static data retention. However, the 6T bit cell has several drawbacks in modern systems, which includes its large transistor count. In order to provide full CMOS logic compatibility a gain-cell (GC)-embedded DRAM (eDRAM) consisting of 3-transistor (3T), GC-eDRAMs which provides a reduced silicon footprint, along with inherent two-port functionality, nonratioed circuit operation, and very low static leakage currents from VDD to GND. With the benefit of read and write access, we modify the 8-TSRAM cell as 3-T SRAM cell with transmission gate that reduces the read and write time access with comparatively low power and eliminating the usage of signal booster. In this paper we designed the 3T GC cell by using MICROWIND/DSCH 180 nm technology and simulation results obtained by using HSPICE 180 nm technology. Key Words: Low power, Gain cell (GC), 3T (3 Transistor), SRAM, I.INTRODUCTION Today world aims in designing low power devices due to the rampant usage of portable battery powered gadgets. Scaling of MOS technology creates new challenges to the SRAM circuit design, mainly leakage power and stability. SRAM design furnishes an approach towards reduces the hold power dissipation devices due to the uncontrolled usage of portable battery powered gadgets. . The proposed cell has similar structure to conventional 6T SRAM cell with the addition of two buffer transistors, one tail transistor and one complementary word line. Dueto stacking effect, the proposed cell achieves lower power dissipation. In this paper, impact of process parameters variations on various design metrics of the proposed cell are presented and compared with conventional differential 6T (D6T),transmission gate based 8T (TG8T) and single ended 8T (SE8T) SRAM cells. Impact of process variation, like threshold voltage and length, on different design metrics of an SRAM cell like, read static noise margin (RSNM), read access time(TRA) and write access time (TWA) are also presented. In deep submicron technology, system-on-chip (SoC) products requires a high speed memory to support increased storage capability. Furthermore static random access memory (SRAM) is widely used for SoC products. Static Random Access Memories (SRAMS) would utilized Likewise cache memory which need aid inserted to microprocessor, System-on-Chip (SoC), Network-on-Chip (NoC) modules. This will be because of those certainty that they would quick contrasted with eDRAM (such Likewise DRAM) Furthermore primary memory (DRAM) [1].They need to be created on the same die of a processor. Concerning illustrations expressed by ITRS, 90% of the processor's chip region is possessed by SRAM [2].increase in processor's speed has risen in recent years, whereas memory speed ...

show abstract

A Highly-Stable Nanometer Memory for Low-Power Design

Cited by 23 publications

References 7 publications

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

A data-aware write-assist 10T SRAM cell with bit-interleaving capability

Design of 3T Gain Cell for Ultra Low Power Applications

Contact Info

Product

Resources

About