Data stability, write ability and leakage power are major concerns in submicron static random access memory (SRAM) cell design. This paper presents an 11T SRAM cell with differential write and single-ended read. Proposed cell offers improved write ability by interrupting its ground connection during write operation. Separate read buffer provides disturb-free read operation. Characteristics are obtained from HSPICE simulation using 32[Formula: see text]nm high-performance predictive technology model. Simulation results show that the proposed cell achieves 4.5[Formula: see text] and 1.06[Formula: see text] higher read static noise margin (RSNM) as compared to conventional 6T (C6T) and PNN-based 10T cells, respectively, at 0.4[Formula: see text]V. Write static noise margin (WSNM) of the proposed design is 1.65[Formula: see text], 1.71[Formula: see text] and 1.77[Formula: see text] larger as compared to those of C6T, PPN-based 10T and PNN-based 10T cells, respectively, at 0.4V. Write “1” delay of the proposed cell is 0.108[Formula: see text] and 0.81[Formula: see text] as those of PPN10T and PNN10T cells, respectively. Proposed circuit consumes 1.40[Formula: see text] lesser read power as compared to PPN10T cell at 0.4[Formula: see text]V. Leakage power of the proposed cell is 0.35[Formula: see text] of C6T cell at 0.4[Formula: see text]V. Proposed 11T cell occupies 1.65[Formula: see text] larger area as compared to that of conventional 6T.

Cell stability is becoming an important design concern as process technology continues to scale down. In this paper, we present a single-ended 10T SRAM cell that improves simultaneously both read static noise margin (RSNM) and write static noise margin (WSNM) by employing separate read buffer and power gating transistors, respectively. The cross-point write structure of the proposed cell facilitates bit-interleaved architecture to enhance soft-error immunity. Simulation is done on 65-nm CMOS technology on Cadence. Simulation results show that the RSNM of the proposed SRAM cell is 2.78 times and 1.47 times higher than those of the conventional 6T and Schmitt trigger-based 10T (ST-2) cells, respectively, at 0.4 V. The WSNM of the proposed design is 5.14 times larger than that of the two-port disturbfree 9T (TPDF9T) cell (without write assist) at 0.4 V. Write delay of the proposed cell is 77.56% less than that of the TPDF9T cell at 0.4 V. Leakage power dissipation of the proposed SRAM cell is 0.89 times that of the ST-2 cell at 0.4 V. The proposed cell occupies 1.34 times more area than the conventional 6T cell.

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