A Highly Stable 10T SRAM Cell for Low Power Applications

Mansore, S. R.; Naik, Amit

doi:10.1109/otcon56053.2023.10113962

2022 OPJU International Technology Conference on Emerging Technologies for Sustainable Development (OTCON) 2023

DOI: 10.1109/otcon56053.2023.10113962

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A Highly Stable 10T SRAM Cell for Low Power Applications

S. R. Mansore¹,

Amit Naik²

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An all-passive Si₃N₄ optical row decoder circuit for addressable optical RAM memories

Simos,

Moschos,

Fotiadis

et al. 2023

J. Phys. Photonics

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In this work we experimentally demonstrate a Si 3 N 4 photonic integrated circuit which offers row decoding and RAM addressing functionalities. The passive integrated structure comprises a MRR-based wavelength filtering bank scheme in a 2 × 4 configuration, which reveals a suppression ratio in the range of 12–25 dB. The performance of the optical circuit has been evaluated in a system-level testbed, where successful addressing in one RAM row has been achieved. Error-free operation has been accomplished for all cases under study, with the whole row decoder system’s performance to offer a total power penalty of 2.5 dB.

show abstract

An all-passive Si₃N₄ optical row decoder circuit for addressable optical RAM memories

Simos,

Moschos,

Fotiadis

et al. 2023

J. Phys. Photonics

View full text Add to dashboard Cite

show abstract

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A Highly Stable 10T SRAM Cell for Low Power Applications

Cited by 1 publication

References 16 publications

An all-passive Si₃N₄ optical row decoder circuit for addressable optical RAM memories

An all-passive Si₃N₄ optical row decoder circuit for addressable optical RAM memories

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A Highly Stable 10T SRAM Cell for Low Power Applications

Cited by 1 publication

References 16 publications

An all-passive Si3N4 optical row decoder circuit for addressable optical RAM memories

An all-passive Si3N4 optical row decoder circuit for addressable optical RAM memories

Contact Info

Product

Resources

About

An all-passive Si₃N₄ optical row decoder circuit for addressable optical RAM memories

An all-passive Si₃N₄ optical row decoder circuit for addressable optical RAM memories