A 32 nm Read Disturb-free 11T SRAM Cell with Improved Write Ability

Mansore, S. R.; Gamad, R. S.; Mishra, D. K.

doi:10.1142/s021812662050067x

Cited by 11 publications

(7 citation statements)

References 20 publications

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“…One of the suggested solutions to the power dissipation problem is to scale back the power supply, but the reliability of the SRAM cell poses another challenge in this. Besides this, issues like data stability, delay and high sensitivity to process variation [7][8][9][10][11][12] also contributes to overall performance of SRAM. and two PMOS (PM 3 and PM 4 ) transistors.…”

Section: Related Workmentioning

confidence: 99%

WITHDRAWN: Low Leakage Variation SRAM Cell with Improved Stability for IOT Applications

Rawat

Kumar

2022

Preprint

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The typical memory for very large scale integrated (VLSI) circuits has traditionally been static random access memory (SRAM). This is so because SRAM is a speedier technology than the ones that were previously mentioned. SRAM, however, has a high power consumption rate. Due to its importance in the memory architecture, it is crucial to lower the power consumption of SRAM cells. This literature review's major goal is to provide innovative and effective strategies for creating low power SRAM cells. This study provides several circuit topologies and methodologies to compute stability, leakage current, delay, and power, as well as novel techniques for designing SRAM cells based on eight transistors (8T). The static random access memory (SRAM) is frequently chosen over dynamic random access memory (DRAM) due to faster speed and lower power consumption. It is named static since no modification or action, i.e. refreshing, is required to maintain the data intact. The leakage current in SRAM, however, frequently rises and impairs its performance when technology nodes are scaled down. Voltage scaling, which also impacts the stability and latency of SRAM, is chosen as a solution to this problem. In this study, a separate (isolated) read port is employed to increase read stability while a negative bit-line (NBL) write aid circuit is used to improve write capability. In terms of write static noise margin (WSNM), write latency, read static noise margin (RSNM), and other metrics, the suggested design has been compared to state-of-the-art work. The following is how the paper is divided into sections: 1. Introduction. Section 2 describes related work. The suggested work is in section 3. Results and discussion are included in section 4 and section 5 Conclusions.

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Section: Related Workmentioning

confidence: 99%

WITHDRAWN: Low Leakage Variation SRAM Cell with Improved Stability for IOT Applications

Rawat

Kumar

2022

Preprint

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“…A cell arrangement having nine transistors (NTV 9T) was proposed with an L-shaped layout, different from the usual rectangle shape [38]. To avoid the sharing of RWLA signal among the neighbouring cells, the layout for the cell is asymmetric.…”

Section: Ntv 9t Sram Cellmentioning

confidence: 99%

“…The cell uses transistors-N5, N6, and N7 to dissociate RBL from the storage node. This SRAM cell can have a notable increase in the sensing delay, when compared with the other cells having a separate read port, due to its enhanced current through the cell [38]. For read operation of the cell, RWLA and RWLB signals are enabled whereas for the write operation, signal WWL is activated.…”

Section: Ntv 9t Sram Cellmentioning

confidence: 99%

A single ended, single port configuration based 9 T SRAM cell for stability enhancement

Singhal,

Rawat,

Mittal

et al. 2023

Phys. Scr.

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The growing demand for power efficient devices and high-density memories has pushed researchers to develop low power SRAMs. The main objective for these researches is to reduce power consumption and enhances battery life and scaling of technology node. Consequently, in this paper a 9T SRAM bit cell with enhanced stability and single ended, single port configuration is proposed. The cell is designed and simulated at 180 nm technology node with a voltage supply of 1V. The cell proposed has low power consumption owing to single bitline, higher read stability due to isolated read port, better write margin due to disconnected feedback connection and resistant to soft errors because of half select disturbance free architecture. To assess the performance of the proposed cell its performance is compared against existing 6T, 8T, 9TST, SB 9T, TRD 9T, and NTV 9T bit cells. The HSNM (RSNM) and WM values for the proposed cell are equal to 364 mV and 368 mV respectively. The cell is designed to be half select disturbance free and supports bit interleaving. The reliability of the proposed cell is further analysed for local, global and temperature variation. While, the area footprint for the cell is 24.91 µm2.

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“…Usually, soft errors occur in burst, impacting consecutive bit cell. Therefore, to ensure a cell's reliability against soft error, various researchers [47,65,66] have reported bit interleaving (BI) as an effective method. In BI continuous bits of single words are segregated by placing them separately.…”

Section: Half Select Disturbance and Soft Error Resiliencementioning

confidence: 99%

A comprehensive analysis of different 7T SRAM topologies to design a 1R1 W bit interleaving enabled and half select free cell for 32 nm technology node

Rawat

Mittal

2022

Proc. R. Soc. A.

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In this paper, a single-ended, dual port, 1R1 W seven transistor-based static random access memory bit cell is presented. The cell is designed based on a detailed review of various pre-existing 7T cells. All the cells in the paper are evaluated at 32 nm technology and supply voltage of 0.8 V. The static analysis reveals that the hold/read noise margins for the proposed cell are 324 mV each, whereas the write margin is 488 mV. Successful read and write operation for the cell requires a pulse-width of 5 ps and 0.14 ns, respectively. The temperature variation and process corner analysis are used to justify the reliability for the proposed cell. The former analysis yields 0.15 and 0.24 mV/°C variation in the HSNM/RSNM, and WM for the cell. The current ratio for the cell is comparatively higher than other cells. The leakage power consumption for the cell is 256 pW, while its read and write power consumption are 6 µW and 1.9 µW, respectively. Also, the cell is half select disturbance-free and therefore supports bit-interleaving. This ensures the increased reliability for the cell. All the aforementioned merits for the cells are achieved with a minimal layout area of 0.553 µm 2 .

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A 32 nm Read Disturb-free 11T SRAM Cell with Improved Write Ability

Cited by 11 publications

References 20 publications

WITHDRAWN: Low Leakage Variation SRAM Cell with Improved Stability for IOT Applications

WITHDRAWN: Low Leakage Variation SRAM Cell with Improved Stability for IOT Applications

A single ended, single port configuration based 9 T SRAM cell for stability enhancement

A comprehensive analysis of different 7T SRAM topologies to design a 1R1 W bit interleaving enabled and half select free cell for 32 nm technology node

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