A 600 MHz superscalar RISC microprocessor with out-of-order execution

Abstract

A six-issue, four-fetch, out-of-order execution, 6OOMHz Alpha microprocessor achieves an estimated 40SpecInt95,60SpecFP95 and 1800MB/s on McCalpin Stream. The 16.7x18.8mmz die contains 15.2M transistors and dissipates an estimated 72W. It is in 2.0V, 6-metal, 0.35pm CMOS with CMP planarization (Table 1) [ll. The chip is in a 587-pin ceramic IPGA with 198 pins for VDD/ VSS that includes a CuW heat slug for low thermal resistance between die and detachable heat sink. An on-chip PLL performs frequency multiplication of a differential PECL reference and synchronizes I/O by phase-aligning a CPU clock to the reference. Figure 1 is a detailed floorplan of the chip. Figure 2 depicts a blockf pipeline diagram of major sections and functions.The instruction fetcher ( Figure 3) reads four instructions per cycle plus a next-address pointer from a 64kB, 2-way pseudo-set associative, virtual instruction cache. The next-address pointer predicts the address of the subsequent four instructions and indexes the cache in the next cycle. In parallel, a branch predictor resolves the prediction. It contains three tables: a PC-indexed prediction table, a path-indexed prediction table, and a pathindexed table that dynamically chooses one of the former two predictions, based on the success of previous predictions. Fetched instructions are dispatched to integedmemory (INT/ MEM) and floating point (FP) pipelines, issued and executed outof order and retired in order. During dispatch, register specifiers are renamed to eliminate false dependencies by two twelve-port register mappers that dynamically map the architectural registers into a pool of physical registers (80 integer and 72 FP). Resulting map state is retained in an array until the instruction retires. Pre-retire map state is used to generate alist of remaining free physical registers. Buffered map state is restored when the CPU is redirected following a branch mispredict or exception.Mapped instructions enter a 20-entry INTMEM or a 15-entry FP issue queue. The INTMEM queue arbiter identifies the 4 oldest data-ready instructions. They issue to the integer execution unit (EBOX) and are removed from the INTMEM queue. Similarly, the FP queue issues the 2 oldest data-ready instructions to the FP execution unit (FBOX) and removes them from the FP queue.The EBOX (Figure 4) is divided into two clusters, CLO and CL1; each cluster contains 2 independent execution pipelines surrounding an 80-entry register file. Coherency between the two register file copies is maintained by broadcasting results across intercluster buses. Each of the four pipelines executes and bypasses arithmetic and logical operations in one cycle. Bypassed results between clusters take an additional cycle. The upper pipelines handle branches and shifts; CLO contains a pipelined multimedia engine (3-cycle latency) and CL1 contains a pipelined multiplier (7-cycle latency). The lower pipelines handle displacement address calculations for memory operations. The FBOX contains 2 independent execution pipelines surrounding a 72-en...

Modeling of coplanar waveguide for buffered clock tree

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“…The second criterion can be mathematically formulated as (15) with relationship between T0 and T1 defined by (16): (16) where (16) is derived from (13). In addition to temperatures, (15) and (16) require knowledge of runtime power, Rt, τ and Ta.…”

Near-optimal precharging in high-performance nanoscale CMOS caches

“…Moreover, clocked precharging requires precise timing on the precharge clock which is often difficult to engineer. Therefore, recent designs [7] advocate static pull-up for the performance-critical L1 caches. We assume static pull-up for the base cache configuration in this paper.…”

“…In highly speculative modern processors, instructions that are dependent on a cache access are speculatively issued assuming that the data from the cache access will be available in a certain cycle. This technique is called load hit speculation [7,9,23]. However, uncertainty in the cache latency can cause additional squashes and reissues of the speculatively-issued instructions.…”

“…Uncertain Load Latency and Instruction Issue: Modern highly speculative superscalar processors including the MIPS R10000, the Alpha 21264 and the Pentium 4, perform load hit speculation [7,9,23]. In general, there is a non-zero delay between instruction issue and execution.…”