No abstract

Leaf aging is a highly regulated developmental process, which is also influenced profoundly by diverse environmental conditions. Accumulating evidence in recent years supports that plant responsiveness to abiotic stress is intimately related with leaf longevity. However, molecular mechanisms underlying the signaling crosstalks and regulatory schemes are yet unknown. In this work, we demonstrate that an abscisic acid (ABA)-responsive NAC transcription factor VND-INTERACTING2 (VNI2) integrates ABA-mediated abiotic stress signals into leaf aging by regulating a subset of COLD-REGULATED (COR) and RESPONSIVE TO DEHYDRATION (RD) genes. The VNI2 gene was induced by high salinity in an ABA-dependent manner. In addition, spatial and temporal expression patterns of the VNI2 gene are correlated with leaf aging and senescence. Accordingly, leaf aging was delayed in transgenic plants overexpressing the VNI2 gene but significantly accelerated in a VNI2-deficient mutant. The VNI2 transcription factor regulates the COR and RD genes by binding directly to their promoters. Notably, transgenic plants overexpressing the COR or RD genes exhibited prolonged leaf longevity. These observations indicate that the VNI2 transcription factor serves as a molecular link that integrates plant responses to environmental stresses into modulation of leaf longevity.

Deep-submicron CMOS designs have resulted in large leakage energy dissipation in microprocessors. While SRAM cells in onchip cache memories always contribute to this leakage, there is a large variability in active cell usage both within and across applications. This paper explores an integrated architectural and circuitlevel approach to reducing leakage energy dissipation in instruction caches. We propose, gated-V dd , a circuit-level technique to gate the supply voltage and reduce leakage in unused SRAM cells. Our results indicate that gated-V dd together with a novel resizable cache architecture reduces energy-delay by 62% with minimal impact on performance.

Deep-submicron CMOS designs maintain high transistor switching speeds by scaling down the supply voltage and proportionately reducing the transistor threshold voltage. Lowering the threshold voltage increases leakage energy dissipation due to subthreshold leakage current even when the transistor is not switching. Estimates suggest a five-fold increase in leakage energy in every future generation. In modern microarchitectures, much of the leakage energy is dissipated in large on-chip cache memory structures with high transistor densities. While cache utilization varies both within and across applications, modern cache designs are fixed in size resulting in transistor leakage inefficiencies. This paper explores an integrated architectural and circuit-level approach to reducing leakage energy in instruction caches (icaches). At the architectural level, we propose the Dynamically ResIzable i-cache (DRI i-cache), a novel i-cache design that dynamically resizes and adapts to an application's required size. At the circuit-level, we use gated-V dd , a mechanism that effectively turns off the supply voltage to, and eliminates leakage in, the SRAM cells in a DRI i-cache's unused sections. Architectural and circuit-level simulation results indicate that a DRI i-cache successfully and robustly exploits the cache size variability both within and across applications. Compared to a conventional i-cache using an aggressively-scaled threshold voltage a 64K DRI i-cache reduces on average both the leakage energy-delay product and cache size by 62%, with less than 4% impact on execution time.

Deep-submicron CMOS designs have resulted in large leakage energy dissipation in microprocessors. While SRAM cells in onchip cache memories always contribute to this leakage, there is a large variability in active cell usage both within and across applications. This paper explores an integrated architectural and circuitlevel approach to reducing leakage energy dissipation in instruction caches. We propose, guted-vdd, a circuit-level technique to gate the supply voltage and reduce leakage in unused SRAM cells.our results indicate that gated-Vdd together with a novel resizable cache architecture reduces energy-delay by 62% with minimal impact on performance.