A 60dB gain and 4dB noise figure CMOS V-band receiver based on two-dimensional passive G&lt;inf&gt;m&lt;/inf&gt;-enhancement

Wang, Ning-Yi; Wu, Hao; Liu, Jenny Yi-Chun; Lu, Jian; Hsieh, Hsieh-Hung; Wu, Po-Yi; Jou, Chewn-Pu; Chang, Mau-Chung Frank

doi:10.1109/rfic.2011.5940603

Cited by 7 publications

(6 citation statements)

References 5 publications

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“…The overall 8mW power of the proposed receiver is 3∼6 times lower than all the rest receiver designs at 60GHz. Moreover, compared to the previous works in [1], [2], [8], the proposed receiver shows the highest conversion gain, best NF and smallest chip area.…”

Section: Measurement Resultsmentioning

confidence: 78%

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An 8mW ultra low power 60GHz direct-conversion receiver with 55dB gain and 4.9dB noise figure in 65nm CMOS

Shang

Cai

Wei

et al. 2012

2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)

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Section: Measurement Resultsmentioning

confidence: 78%

“…As such, ultra low power receiver design is desirable but also challenging for 60GHz CMOS receiver design. Recently, several excellent 60GHz CMOS direct-conversion receivers front-end have been reported [1], [2]. However, all these 60GHz directconversion receivers have high power consumption from 50.2mW to 34mW.…”

Section: Introductionmentioning

confidence: 99%

An 8mW ultra low power 60GHz direct-conversion receiver with 55dB gain and 4.9dB noise figure in 65nm CMOS

Shang

Cai

Wei

et al. 2012

2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)

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“…Low-power design techniques, such as the use of highand compact passive devices and transistors operated at the subthreshold region, have to be explored for the direct-conversion receiver design at 60 GHz. A low-power one-branch 60-GHz receiver in 65-nm CMOS was reported in [14]. Due to 2-D passive -enhancement, it can achieve a high gain without sacrificing extra power in the LNA.…”

Section: Introductionmentioning

confidence: 99%

“…Compared to the heterodyne receiver, the direct-conversion receiver has a lower power requirement due to simpler structure with less building blocks. As such, direct-conversion receivers have been explored in 60 GHz [2], [3], [5], [6], [13], [14], which includes key building blocks such as the low-noise amplifier (LNA), mixer, variable-gain amplifier (VGA), and baseband. Moreover, many studies [2], [3], [6], [13], [14] assume one branch direct-conversion receiver.…”

Section: Introductionmentioning

confidence: 99%

“…As such, direct-conversion receivers have been explored in 60 GHz [2], [3], [5], [6], [13], [14], which includes key building blocks such as the low-noise amplifier (LNA), mixer, variable-gain amplifier (VGA), and baseband. Moreover, many studies [2], [3], [6], [13], [14] assume one branch direct-conversion receiver. In [1] and [4], two in-phase/quadrature (I/Q) branches are deployed in a 60-GHz transceiver with quadrature phase-shift keying (QPSK) modulation for higher spectrum efficiency at the cost of more power.…”

Section: Introductionmentioning

confidence: 99%

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Design of Ultra-Low-Power 60-GHz Direct-Conversion Receivers in 65-nm CMOS

Cai

Shang

et al. 2013

IEEE Trans. Microwave Theory Techn.

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This paper has explored an ultra-low-power design of two 60-GHz direct-conversion receivers in a 65-nm CMOS process for single-channel and multi-channel applications under the IEEE 802.15.3c standard, respectively. One subthreshold biasing 0.4-V transconductance mixer is designed with a compact quadrature hybrid coupler (160 m 210 m with measured 3-dB intrinsic loss) in receivers to achieve low power (8 mW for single channel and 12.4 mW for multi-channel) and high gain (55 dB for single channel and 62-dB for multi-channel). One three-stage low-noise amplifier employs high-passive matchings. A double-layer-stacked inductor is utilized for matching in the single-channel receiver and a high-impedance transmission line is utilized for matching in the multi-channel receiver, respectively. In addition, one new modified Cherry-Hooper amplifier is applied for the variable-gain amplifier design to achieve high gain-bandwidth product and high power efficiency. The single-channel receiver is implemented with 0.34-mm chip area. It is measured with a power consumption of 8 mW, a minimum single-sideband noise figure (NF) of 4.9 dB, a 3-dB bandwidth of 3.5 GHz, and a maximum conversion gain of 55 dB. The multi-channel receiver is implemented with 0.56-mm chip area. It is measured with a power consumption of 12.4 mW, a 3-dB bandwidth of 8 GHz (59.5 67.5 GHz), and a maximum conversion gain of 62 dB. The measurement results show that the two demonstrated 60-GHz direct-conversion receivers can achieve high gain and low NF with ultra-low power in 65-nm CMOS.

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A low-overhead self-healing embedded system for ensuring high yield and long-term sustainability of 60GHz 4Gb/s radio-on-a-chip

Tang

Hsiao

Murphy

et al. 2012

2012 IEEE International Solid-State Circuits Conference

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A 60dB gain and 4dB noise figure CMOS V-band receiver based on two-dimensional passive G<inf>m</inf>-enhancement

Cited by 7 publications

References 5 publications

An 8mW ultra low power 60GHz direct-conversion receiver with 55dB gain and 4.9dB noise figure in 65nm CMOS

An 8mW ultra low power 60GHz direct-conversion receiver with 55dB gain and 4.9dB noise figure in 65nm CMOS

Design of Ultra-Low-Power 60-GHz Direct-Conversion Receivers in 65-nm CMOS

A low-overhead self-healing embedded system for ensuring high yield and long-term sustainability of 60GHz 4Gb/s radio-on-a-chip

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