A 62 mV 0.13 $\mu$m CMOS Standard-Cell-Based Design Technique Using Schmitt-Trigger Logic

Lotze, Niklas; Manoli, Yiannos

doi:10.1109/jssc.2011.2167777

Cited by 137 publications

(51 citation statements)

References 36 publications

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“…However, quantifying such a negative impact on digital switching is very challenging for two fundamental reasons [18]. First, the switching failure of a given logic circuit is almost always caused by a group of several transistors that gradually experience increases in V th ; therefore, it is very difficult to attribute the overall logic failure of a circuit to a single gate.…”

Section: Bti-induced Error Probability In Cmos Switchesmentioning

confidence: 99%

“…In fact, for a given logic gate, as long as its output voltage level can be correctly interpreted by its receiving circuit, any input voltage level is theoretically acceptable. To overcome these issues, we use a modeling approach based on the voltage transfer curve (VTC) analysis proposed in [19] and further developed in [18]. In this method, the amount of headroom to a switching failure is measured with the worst-case static noise margin (SNM) present in the gate pair, which can be determined using the DC noise source configuration shown in Figure 2a,b, or equivalently from a butterfly plot shown in Figure 2c.…”

Section: Bti-induced Error Probability In Cmos Switchesmentioning

confidence: 99%

“…Intuitively, the larger the values of W 1 and W 2 , the better the switching performance is. As in both [18] and [19], the exact threshold value of W 1 and W 2 , as well as their corresponding threshold values of V * th can be determined empirically. In this paper, we define that the switching failure happens when the VTC asymmetry ratio γ exceeds 0.1, where γ is defined as…”

Section: Bti-induced Error Probability In Cmos Switchesmentioning

confidence: 99%

“…For gates with more than one input, multiple possible VTCs exist depending on the input configuration. As suggested in [18], we solve this problem by considering only gate combinations that are expected to be critical, due to their topology. For example, given the common logic gates, such as NAND2 and NOR2, an obvious choice for the critical VTC will be the input combination of a weak low and a weak high values due to the stacked transistors in the corresponding output path.…”

Section: Bti-induced Error Probability In Cmos Switchesmentioning

confidence: 99%

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Optimally Fortifying Logic Reliability through Criticality Ranking

et al. 2015

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With CMOS technology aggressively scaling towards the 22-nm node, modern FPGA devices face tremendous aging-induced reliability challenges due to bias temperature instability (BTI) and hot carrier injection (HCI). This paper presents a novel anti-aging technique at the logic level that is both scalable and applicable for VLSI digital circuits implemented with FPGA devices. The key idea is to prolong the lifetime of FPGA-mapped designs by strategically elevating the V DD values of some LUTs based on their modular criticality values. Although the idea of scaling V DD in order to improve either energy efficiency or circuit reliability has been explored extensively, our study distinguishes itself by approaching this challenge through an analytical procedure, therefore being able to maximize the overall reliability of the target FPGA design by rigorously modeling the BTI-induced device reliability and optimally solving the V DD assignment problem. Specifically, we first develop a systematic framework to analytically model the reliability of an FPGA LUT (look-up table), which consists of both RAM memory bits and associated switching circuit. We also, for the first time, establish the relationship between signal transition density and a LUT's reliability in an analytical way. This key observation further motivates us to define the modular criticality as the product of signal transition density and the logic observability of each LUT. Finally, we analytically prove, for the first time, that the optimal way to improve the overall reliability of a whole FPGA device is to fortify individual LUTs according to their modular criticality. To the best of our knowledge, this work is the first to draw such a conclusion.

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Section: Bti-induced Error Probability In Cmos Switchesmentioning

confidence: 99%

Section: Bti-induced Error Probability In Cmos Switchesmentioning

confidence: 99%

Section: Bti-induced Error Probability In Cmos Switchesmentioning

confidence: 99%

Section: Bti-induced Error Probability In Cmos Switchesmentioning

confidence: 99%

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Optimally Fortifying Logic Reliability through Criticality Ranking

et al. 2015

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“…Therefore in this paper, we proposed CMOS Schmitt Trigger circuit which is capable to operate in low voltage (0.8V-1.5V) at high capacitance, less propagation delay and stable hysteresis width. By lowering the supply voltage is an effective method to achieve low power operation [3]- [4]. …”

Section: Introductionmentioning

confidence: 99%

Low voltage CMOS Schmitt Trigger in 0.18μm technology

Arith¹,

Idris²,

Zainudin³

et al. 2013

IOSRJEN

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This paper presents the effect of source voltage on performance of proposed Schmitt Trigger circuit. The proposed circuit was designed based on Conventional Schmitt Trigger by manipulating the arrangement of transistors and the width-length ratio. The simulation results have been carried out based on Mentor Graphics software in term of propagation delay. The circuit layout has been designed and checked by using design rule check (DRC) and layout versus schematic (LVS) method. From these results, the proposed full swing CMOS Schmitt Trigger was able to operate at low voltage (0.8V-1.5V)

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Fpga

2016

Physics and Technology of Crystalline Oxide Semiconductor CAAC‐IGZO

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A 62 mV 0.13 $\mu$m CMOS Standard-Cell-Based Design Technique Using Schmitt-Trigger Logic

Cited by 137 publications

References 36 publications

Optimally Fortifying Logic Reliability through Criticality Ranking

Optimally Fortifying Logic Reliability through Criticality Ranking

Low voltage CMOS Schmitt Trigger in 0.18μm technology

Fpga

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