A 630 Mbps non-binary LDPC decoder for FPGA

Abstract

Abstract-A high-speed non-binary LDPC decoder based on Trellis Min-Max algorithm with layered schedule is presented. The proposed approach compresses the check-node output messages into a reduced set, decreasing the number of messages sent to the variable node. Additionally, the memory resources from the layered architecture are reduced. The proposed decoder was implemented for the (2304,2048) NB-LDPC code over GF(16) on a Virtex-7 FPGA and in a 90 nm CMOS process. Our implementation outperforms state-of-the-art NB-LDPC decoder implementations for both technologies, achieving a throughput of 630 and 965 Mbps, respectively.

High-Performance NB-LDPC Decoder With Reduction of Message Exchange

“…In [24] we particularise the proposal in [23] to T-MM algorithm, and we detail a hardware architecture for the CN processor and for a decoder with layered schedule. In this paper we extend the work in [24], and present a modification of the T-MM algorithm that allow us to reduce even more the number of exchanged messages. The CN output messages are split in two arrays: one that compresses the extrinsic information and another which represents the intrinsic one.…”

VLSI algorithms and architectures for non-binary-LDPC decoding

“…Section 6.3.2 extends the explanation of the algorithm proposed in [54] taking as a reference the algorithm reformulated in Section 6.3.1 and also includes an analogy with binary LDPC decoders. Finally, Section 6.3.3 defines the new algorithm (modified T-MM, mT-MM), which is based on an statistical analysis, and gives FER performance results for high-rate NB-LDPC codes over GF (16), GF (32) and GF(64).…”

“…Applying a message compression technique [54], the basic steps of T-MM in the CN and the number of exchanged messages are further reduced without introducing any performance loss compared to the original T-MM algorithm.…”

“…This is due to the reduction of complexity in the I * (a) generation that is the bottleneck in the CN implementation from [53]. In this section we include the proposed CN architecture in a layered decoder with a similar structure to [54].…”

“…In [54] we particularize the proposal in [53] to T-MM algorithm, and we detail a hardware 95 architecture for the CN processor and for a decoder with layered schedule. In this paper we extend the work in [54], and present a modification of the T-MM algorithm that allow us to reduce even more the number of exchanged messages. The CN output messages are split in two arrays: one that compresses the extrinsic information and another which represents the intrinsic one.…”