A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET

Özkaya, İlter; Cevrero, Alessandro; Francese, Pier Andrea; Menolfi, Christian; Morf, Thomas; Brändli, Matthias; Kuchta, Daniel M.; Kull, Lukas; Baks, Christian; Proesel, Jonathan E.; Kossel, Marcel; Luu, Danny; Lee, Benjamin G.; Doany, F. E.; Meghelli, Mounir; Leblebici, Yusuf; Toifl, Thomas

doi:10.1109/jssc.2017.2734913

Cited by 62 publications

(32 citation statements)

References 14 publications

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“…As shown in Figure 3b, improved front-end noise performance is possible by utilizing a low-bandwidth TIA input stage with a relatively large feedback resistor that is followed by an equalizer to achieve the overall desired bandwidth. [9,32,33] The equalizer can be in the form of a continuous-time linear equalizer (CTLE), which provides frequency peaking, or a decision-feedback equalizer that directly subtracts intersymbol interference in the time domain. This topology decouples the noise-bandwidth dependency, with the low BW TIA providing superior noise performance and the equalizer and additional gain stages compensating for the input bandwidth reduction.…”

Section: Tia Input Referred Noisementioning

confidence: 99%

Design Considerations for Energy Efficient DWDM PAM4 Transceivers Employing Avalanche Photodiodes

Kumar

Huang

Zeng

et al. 2020

Laser & Photonics Reviews

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An effective approach to increase per‐fiber bandwidth is to combine per‐wavelength four‐level pulse amplitude modulation (PAM4) with dense wavelength division multiplexing (DWDM). Silicon photonic transceivers based on microring resonator modulators and drop filters can allow for an efficient realization of this. Utilizing avalanche photodiodes (APDs) in the receiver front‐ends of these transceivers can significantly improve sensitivity, allowing for reduced source laser power and overall improved power efficiency. This paper analyzes the optical‐modulation amplitude (OMA) sensitivity of these APD‐based PAM4 receivers in a silicon photonic DWDM link. A comprehensive link budget is considered that takes into account various system losses and relevant noise sources. Modeling with a developed APD that has a maximum 230 GHz gain‐bandwidth product predicts sensitivity improvements at 32 to 64 Gb s−1 PAM4 ranging from 9.8 to 12 dB relative to a conventional p‐i‐n photodiode. Scaling the APD gain‐bandwidth to 310 GHz allows support of 112 Gb s−1 with −13.2 dBm OMA sensitivity at a BER of 2.4×10−4 with an APD gain of 10. Utilizing the presented architecture, link budget analysis predicts a 9.5x reduction in laser power with APDs and that 38 mW source laser optical power can support a four‐channel DWDM link operating at an aggregate 448 Gb s−1 data rate.

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Section: Tia Input Referred Noisementioning

confidence: 99%

Design Considerations for Energy Efficient DWDM PAM4 Transceivers Employing Avalanche Photodiodes

Kumar

Huang

Zeng

et al. 2020

Laser & Photonics Reviews

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“…Then, the input-referred noise is obtained by dividing (1) with the trans-impedance gain R as: Nowadays, in order to take advantage of the CMOS inverter in modern process technology, there has been a lot of approaches to adopt CMOS inverter into analog circuits. This paper focuses on the applications of high-speed analog circuits, and introduces three examples of that, amplifier in optical communication receivers [6,[14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30], high-speed clock and data buffer [13,[31][32][33][34][35][36][37][38][39][40][41], and output driver for high-speed I/O transmitter [13,40,[42][43][44][45][46][47][48][49][50].…”

Section: Cmos Inverter As An Amplifiermentioning

confidence: 99%

“…The resistive-feedback inverter TIA is also able to be combined with inductive peaking technique, to extend the bandwidth with less gain/power penalty. References [19,25] present the inverter TIA with series inductive peaking, which is illustrated in Figure 6a. Since an inductor blocks an instantaneous current flow, it enables sequential charging (or discharging) of the two adjacent capacitances (for example, PD capacitance and self-load at the input node, or self-load and load capacitances at the output node), which leads to a faster transient response.…”

Section: Cmos Inverter As An Amplifiermentioning

confidence: 99%

“…The application of CMOS inverter as an amplifier is not limited to the TIA. Optical receivers presented in [18,19,21,[24][25][26][27] extend the usage of the CMOS inverter to the post limiting amplifier which follows the TIA. In addition, [16,17,30] present resistive-feedback-inverter-based low-noise amplifier (LNA) and variable gain amplifier (VGA), respectively.…”

Section: Cmos Inverter As An Amplifiermentioning

confidence: 99%

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CMOS Inverter as Analog Circuit: An Overview

Bae

2019

JLPEA

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Since the CMOS technology scaling has focused on improving digital circuit, the design of conventional analog circuits has become more and more difficult. To overcome this challenge, there have been a lot of efforts to replace conventional analog circuits with digital implementations. Among those approaches, this paper gives an overview of the latest achievement on utilizing a CMOS inverter as an analog circuit. Analog designers have found that a simple resistive feedback pulls a CMOS inverter into an optimum biasing for analog operation. Recently developed applications of the resistive-feedback inverter, including CMOS inverter as amplifier, high-speed buffer, and output driver for high-speed link, are introduced and discussed in this paper.

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“…Automatic gain control (AGC) potentially reduces jitter and pulse-width distortion under circumstances of large input current swing. Several power-efficient 40-Gb/s and beyond TIAs and RXs implemented in CMOS technology were reported [11,16,17,18,19]. In these designs, series or shunt inductive peaking techniques were employed for bandwidth extension.…”

Section: Introductionmentioning

confidence: 99%

A low-noise 71-dBΩ transimpedance 31-GHz bandwidth optical receiver with automatic gain control in 0.13-µm SiGe BiCMOS

Zhang

Chen

et al. 2019

IEICE Electron. Express

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A low-noise high-gain high-speed optical receiver is fabricated in 0.13-µm SiGe BiCMOS. The transimpedance amplifier incorporating a differential common-base shunt-feedback topology features isolation to input capacitance and high transimpedance limit. Specifically, a comprehensive analytical expression of the input-referred noise current power spectral density of the transimpedance amplifier is derived and investigated, which provides insights for noise optimization. Additionally, the linearity of intermediate stages is improved by a modified variable-gain amplifier operating with automatic gain control. The measured results show a low noise level of 14.5 pA √ Hz, 31-GHz bandwidth, and the maximum 71-dBΩ transimpedance.

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A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET

Cited by 62 publications

References 14 publications

Design Considerations for Energy Efficient DWDM PAM4 Transceivers Employing Avalanche Photodiodes

Design Considerations for Energy Efficient DWDM PAM4 Transceivers Employing Avalanche Photodiodes

CMOS Inverter as Analog Circuit: An Overview

A low-noise 71-dBΩ transimpedance 31-GHz bandwidth optical receiver with automatic gain control in 0.13-µm SiGe BiCMOS

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