A 64-Point Fourier Transform Chip for High-Speed Wireless LAN Application Using OFDM

Abstract

Abstract-In this paper, we present a novel fixed-point 16-bit word-width 64-point FFT/IFFT processor developed primarily for the application in an OFDM-based IEEE 802.11a wireless LAN baseband processor. The 64-point FFT is realized by decomposing it into a two-dimensional structure of 8-point FFTs. This approach reduces the number of required complex multiplications compared to the conventional radix-2 64-point FFT algorithm. The complex multiplication operations are realized using shift-and-add operations. Thus, the processor does not use a two-input digital multiplier. It also does not need any RAM or ROM for internal storage of coefficients. The proposed 64-point FFT/IFFT processor has been fabricated and tested successfully using our in-house 0.25-m BiCMOS technology. The core area of this chip is 6.8 mm 2 . The average dynamic power consumption is 41 mW at 20 MHz operating frequency and 1.8 V supply voltage. The processor completes one parallel-to-parallel (i.e., when all input data are available in parallel and all output data are generated in parallel) 64-point FFT computation in 23 cycles. These features show that though it has been developed primarily for application in the IEEE 802.11a standard, it can be used for any application that requires fast operation as well as low power consumption.

Fast Fourier Transform Processors: Implementing FFT and IFFT Cores for OFDM Communication Systems

“…The FFT/IFFT becomes one of the most critical modules in OFDM transceivers. In fact, the most computationally intensive parts of an OFDM system are the IFFT in the transmitter and the Viterbi decoder in the receiver (Maharatna et al, 2004). The FFT is the second computationally intensive part in the receiver.…”

“…(Jung et al, 2005) 64 Pipeline-MDC r-2 DIT WLAN (Maharatna et al, 2004) 64 Pipeline r-2 DIT WLAN (Serrá et al, 2004) 64 Monoprocessor r-2 DIT WLAN (Lin et al, 2005) 128 Pipeline-MRMDF MR 2/2 3 DIF UWB (Saberinia, 2006) 128 Pipeline-BRMDC r-2 DIF UWB (Lee et al, 2006) 128 Pipeline-SDF r-2 4 DIF UWB (Liu et al, 2007) 64/128 Pipeline 8-path DF MR DIF UWB (Cortés et al, 2007) 128 Pipeline r-2 4 DIF UWB (Bidet et al, 1995) 8192 Pipeline-SDC r-4/2 DIF DVB-T (Lin, Liu & Lee, 2004) 8192 Parallel r-2 3 DIT DVB-T (Wang et al, 2005) 2/8 K Pipeline-SDF r-4/2 DIF DVB-T ( Lenart & Owal, 2006) 2/4/8 K Pipeline-SDF r-2 2 DIF DVB-T/H (Lee & Park, 2007) 8K Pipeline-SDF BD DVB-T (He & Torkelson, 1998) 1024 Pipeline-SDF r-2 2 DIF OFDM (Kuo et al, 2003) 64-2048 Cached memory r-2 DIT OFDM (Chang & Park, 2004) 1024 Monoprocessor r-4 DIF OFDM (Jiang et al, 2004) 64 Parallel r-2 DIT OFDM (Lin, Lin, Chen & Chang, 2004) 64 Pipeline r-2 DIF MIMO (Rudagi et al, 2010) 64 Pipeline r-2 DIT OFDM (Yu et al, 2011) 64 Pipeline r-2 DIF OFDM (Tsai et al, 2011) 64 Pipeline MR OFDM (Turrillas et al, 2010) 32 K Pipeline r-2 k DIF DVB-T2 Table 1. FFT proposals for OFDM systems…”

“…Thus, (Chang & Park, 2004;Cortés et al, 2007;He & Torkelson, 1998;Jiang et al, 2004;Jung et al, 2005;Kuo et al, 2003;Lee et al, 2006;Lin, Lin, Chen & Chang, 2004;Lin et al, 2005;Liu et al, 2007;Maharatna et al, 2004;Saberinia, 2006;Serrá et al, 2004) proposed fixed-point FFTs for N < 8192. Nevertheless, (Wang et al, 2005) also used the fixed-point format for large FFTs.…”

“…Examples of these representations can be found in (He & Torkelson, 1998;Lee & Park, 2007;Lee et al, 2006;Lin, Lin, Chen & Chang, 2004;Lin, Liu & Lee, 2004;Lin et al, 2005;Liu et al, 2007;Maharatna et al, 2004;Tsai et al, 2006). These representations do not help the designer to understand the algorithm fast, therefore, making it difficult to relate it to its HW resources.…”

Low-Power VLSI Implementation of the Inner Receiver for OFDM-Based WLAN Systems

“…Some parts of the present work have been published in discrete and short form [6]- [12]. In this paper we provide a more detailed design description and an integrated view of the complete IRx design process.…”