A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology

Lee, Daeyeal; Chang, Ik Joon; Yoon, Seong Yong; Jang, Joonsuc; Jang, Dong-Hoon; Hahn, Wook-Ghee; Park, Jong-Yeol; Kim, Doogon; Yoon, Chi-Weon; Lim, Byung Su; Min, Byung-Jun; Sung-Won, Yun; Lee, Ji-Sang; Park, Il-Han; Kim, Kyungryun; Yun, Jeong-Yun; Kim, Youse; Cho, Yong-Sung; Kang, Kyung-Min; Joo, Sanghoon; Chun, Jinyoung; Im, Jung-No; Kwon, Sin; Ham, Seokjun; Park, An-Soo; Yu, Jae-Duk; Lee, Nam-Hee; Lee, Tae-Sung; Kim, Moosung; Kim, Hoo-Sung; Song, Ki–Whan; Jeon, Boyoung; Choi, Kihwan; Han, Jin-Man; Kyung, Kye Hyun; Lim, Young‐Hun; Jun, Young-Hyun

doi:10.1109/isscc.2012.6177077

Cited by 27 publications

(9 citation statements)

References 3 publications

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“…A good overview of EEPROM/Flash history was presented at ISSCC2012 (Harari, 2012). Recent data on EEPROM devices shows commercially announced devices at 15 nm (Hynix, IEDM) and 19 nm [Toshiba/ScanDisk (Li et al, 2012; Shibata et al, 2012) and Samsung (Lee et al, 2012)] as well as production of 32 nm devices. From the current EEPROM progress, such devices are expected to migrate to 7 and 11 nm technology nodes; therefore the risk that the industry will not commercially produce a 10 nm floating-gate device is very low.…”

Section: Large-scale Neuromorphic Systemsmentioning

confidence: 99%

Finding a roadmap to achieve large neuromorphic hardware systems

2013

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Neuromorphic systems are gaining increasing importance in an era where CMOS digital computing techniques are reaching physical limits. These silicon systems mimic extremely energy efficient neural computing structures, potentially both for solving engineering applications as well as understanding neural computation. Toward this end, the authors provide a glimpse at what the technology evolution roadmap looks like for these systems so that Neuromorphic engineers may gain the same benefit of anticipation and foresight that IC designers gained from Moore's law many years ago. Scaling of energy efficiency, performance, and size will be discussed as well as how the implementation and application space of Neuromorphic systems are expected to evolve over time.

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Section: Large-scale Neuromorphic Systemsmentioning

confidence: 99%

Finding a roadmap to achieve large neuromorphic hardware systems

2013

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“…Table 2 shows the parameter values used in the experiments. The size of the DRAM in SSD, not only for write buffering but also for SSD metadata store, was set based on a real product [1] and the page read/write times were set using the value presented in [15]. Since PDL requires additional memory space for mapping information between data pages and their respective differential log pages, we decreased its write buffer size by the amount of mapping information, for fair comparison.…”

Section: Evaluation Environmentmentioning

confidence: 99%

Dual region write buffering

Kim

Kang

2015

Proceedings of the 30th Annual ACM Symposium on Applied Computing

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Write buffering not only enables Solid State Drive (SSD) to immediately respond to the write request but also increases the lifespan of the SSD by reducing the amount of data written to the flash memory. However, since the DRAM which is used as a write buffer is volatile, it has a few critical problems such as buffered data loss upon sudden power-off and limited write reduction effect due to the flush commands and synchronous writes from the file system. These problems can be addressed when non-volatile memory (NVRAM) is used, instead of DRAM, as a write buffer. In this paper, we propose a novel Dual-Region Write Buffering (DRWB) scheme that implements logically non-volatile write buffer using large sized DRAM and small capacity capacitor. The DRWB exploits the differential write scheme, which has been developed originally for the write reduction in SSD, to protect data in the write buffer. Experimental results show that the proposed scheme enables us to achieve the same effect with the NVRAM write buffer, in terms of the data reliability, without noticeable performance degradation.

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“…1. At these regions, we have bit-errors during read operations and they are recovered using an error correcting code (ECC) technique in the off-chip controller [2]. In scaled NAND Flash memories, BCH code is widely used for the ECC technique [3].…”

Section: State Re-orderingmentioning

confidence: 99%

“…During programming operations of NAND Flash memories, cell-to-cell interference and F-N tunneling disturbance vary threshold voltages of the E-state cells [1,2]. This narrows the window where threshold voltages (V t 's) of program-state cells can be placed.…”

Section: Introductionmentioning

confidence: 99%

Bit-error rate improvement of TLC NAND Flash using state re-ordering

Chang

Yang

2012

IEICE Electron. Express

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In scaled technologies, large cell-to-cell interference and F-N tunneling disturbance degrade threshold voltage (V t ) window which we can place program states. Moreover, in Triple Layer Cell (TLC) NAND Flash we should place seven program states (P 1~P7 ) in the narrow V t window, incurring large biterror rate (BER). In this paper, we propose a state re-ordering technique to increase the efficiency of V t window utilization in TLC NAND Flash memories. Our simulation results show that under equivalent V t window sizes, the proposed technique provides 12.5~18.4% smaller BER compared to conventional Gray-code mapping.

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A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology

Cited by 27 publications

References 3 publications

Finding a roadmap to achieve large neuromorphic hardware systems

Finding a roadmap to achieve large neuromorphic hardware systems

Dual region write buffering

Bit-error rate improvement of TLC NAND Flash using state re-ordering

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