Bit-error rate improvement of TLC NAND Flash using state re-ordering

Abstract

In scaled technologies, large cell-to-cell interference and F-N tunneling disturbance degrade threshold voltage (V t ) window which we can place program states. Moreover, in Triple Layer Cell (TLC) NAND Flash we should place seven program states (P 1~P7 ) in the narrow V t window, incurring large biterror rate (BER). In this paper, we propose a state re-ordering technique to increase the efficiency of V t window utilization in TLC NAND Flash memories. Our simulation results show that under equivalent V t window sizes, the proposed technique provides 12.5~18.4% smaller BER compared to conventional Gray-code mapping.

Advanced error-prediction LDPC with temperature compensation for highly reliable SSDs

“…In TLC, three pages (1st/2nd/3rd) are stored in one physical page and there are eight possible V TH states per cell [20]. Each page requires two to three reference levels (V Ref ) during read sensing.…”

Hexa-SSD: Overcoming capacitance constraints in SSDs

“…In 2011, a typical 2.5-inch SSD had 256GB capacity, but by 2018, a high-capacity SSD boasted 30TB, expanding by 100× over the past ten years [4,5]. This remarkable growth in the SSD's capacity is thanks to the vertical stacking of layers that break the process scaling limit [6,7,8,9,10] and multi-level cells that store multiple bits in a given transistor [11,12,13,14]. On the other hand, Al(aluminum) and Ta(tantalum)-electrolytic capacitors used in SSDs have increased in density only by tenfold across four decades, approximately a 50× slower rate per year [15].…”

“…, W(12), W(2), W(6), W(18), and W(7).In contrast, Hexa-SSD calculates the write cost for each datum that indicates an increase in the number of dirty pages of the mapping table when it is flushed, and it processes the request with minimum cost first. In this example, the write request W(2) has top priority because its associated mapping table page (m0) is already dirty, and thus it does not add to the number of dirty translation pages.…”

Performance analysis of three-dimensional-triple-level cell and two-dimensional-multi-level cell NAND flash hybrid solid-state drives

“…Moreover, to accomplish further bit cost reduction with 2D-NAND flash memories, multi-level architecture, such as multi-level cell (MLC: 2 bits per cell) and triple-level cell (TLC: 3 bits per cell), has been developed. [7][8][9][10][11][12] Figure 2 shows the difference between MLC and TLC NAND flash. TLC NAND flash achieves 33% lower bit cost than MLC NAND flash.…”