A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation

Abstract

A 7 bit 2 GS/s flash ADC fabricated in a 65nm CMOS process is presented. The proposed cascaded latch interpolation technique achieves a 4 interpolation factor with only dynamic comparators. A background latching-time adjustment scheme utilizing a replica latch array ensures an interpolation capability that is robust to process, voltage and temperature variations. The measured peak INL and DNL of 0.64 LSB and 0.58 LSB, respectively, after comparator offset calibration prove successful interpolation operation. The measured SNDR and SFDR were 38.12 dB and 49.05 dB, respectively, with a 1.08GHz input at 2 GS/s operation while consuming 20.7 mW of total power. This ADC achieves a figure of merit of 157 fJ/conversion-step with a Nyquist input at 2 GS/s.

A 4x Time-Domain Interpolation 6-bit 3.4 GS/s 12.6 mW Flash ADC in 65 nm CMOS

“…This makes the offset between δt comp and δt SR change in a similar manner under PVT variation. Thus, the sizeweighted time offset in the NAND-based SR-Latch is robust to PVT variation in low-to-medium resolution designs and does not need calibration like in [7]. In the TT corner at 27°C, with 1.0V voltage supply, δt comp ≈ δt SR ≈ 7.9 ps where the time reference is achieved by unbalance sizing in the latch.…”

“…However, in the applications where lower power and wider signal bandwidth are requested, a higher interpolation factor larger than two is preferable, which will reduce hardware complexity and related burdens such as input capacitance and clock distribution. A total interpolation factor of 4 is proposed in [7] with a two-stage cascaded latch interpolation technique. But, it requires background calibration in order to eliminate the offset in the 2 nd stage latches, besides the 1 st stage comparators.…”

“…This adds hardware complexity and higher power consumption. This paper reports a time-interpolation flash ADC [8] which achieves the same interpolation factor as [7]. However, the interpolated SR-latches do not require extra calibration or clock control; therefore, the design complexity and hardware overhead is low.…”

A two-step offset calibration in dynamic comparator using body voltage control

“…Since the one least-significant bit (1 LSB = ADC input full scale/2 N , N = ADC resolution) of the ADC decreases with an increase in the ADC resolution, the calibration resolution has to be increased further. The above-mentioned issue is well explained in the authors' papers [4] and [5]. [4] describes a 6-bit resolution ADC, and the number of DFFs required for approximately 3-bit calibration for each comparator was nine.…”

“…One example is the comparator design of the flash ADC. A comparator has been designed with a small size for low power consumption at the cost of an increased offset, and it has been digitally calibrated, which has become a generalized design technique in recent years [4,5,6,7,8]. Nevertheless, flash ADCs still suffer from large hardware overhead since the number of comparators to be calibrated grows exponentially with the ADC resolution.…”