A two-step offset calibration in dynamic comparator using body voltage control

Abstract

An accurate two-step offset calibration technique based on body voltage control for PMOS and NMOS devices is presented for dynamic latch type comparator. An efficient implementation of calibration logic is also introduced. Design issues and the function of the proposed scheme are discussed and simulated in 90 nm CMOS.

Analysis of strong-arm comparator with auxiliary pair for offset calibration

“…Several clock signals (i.e., three clocks in [7,8]) greatly increase the complexity of chip design. The body voltage of the input transistor pair is controlled to tune the current to compensate for input-referred offset [10]. However, it requires a special process to have enough calibration range and resolution.…”