A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die

Ohbayashi, S.; Yabuuchi, Makoto; Kono, Ken; Oda, Yoshimasa; Imaoka, Shingi; Usui, K.; Yonezu, T.; Iwamoto, Takeshi; Nii, Koji; Tsukamoto, Yasumasa; Arakawa, M.; Uchida, Tetsuya; Okada, Michiyo; Ishii, Atsushi; Yoshihara, Tsutomu; Makino, Hiroshi; Ishibashi, Koji; Shinohara, Hirofumi

doi:10.1109/jssc.2007.908004

Cited by 14 publications

(3 citation statements)

References 19 publications

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“…The DVS can be achieved by either lowering V DD [11,57,61], or raising the ground, V SS [2], or both [31]. Many bitcell topologies and design methodologies that employ DVS [25,84,85] have been proposed in recent past to achieve low energy consumption (by operating at or near subthreshold region) and high density, while, ensuring sufficient noise margins and susceptibility to process variations.…”

Section: Introductionmentioning

confidence: 99%

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Robust SRAM Designs and Analysis

Singh¹,

Mohanty²,

Pradhan³

2013

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Section: Introductionmentioning

confidence: 99%

“…Several SRAM bitcell topologies [18,23] and design methodologies [84,85] have been discussed in the literature for 1-port SRAM bitcells, addressing the nanoregime challenges. However, it is a non-trivial task to simultaneously maintain SNM, WAM, and I read in multi-port SRAM bitcells [101].…”

Section: Introductionmentioning

confidence: 99%

Robust SRAM Designs and Analysis

Singh¹,

Mohanty²,

Pradhan³

2013

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“…Several bitcell topologies [3,2] and design methodologies [9,8] are discussed in the current literature for I-port SRAM bitcells, addressing the nano-regime challenges. However, it is a non-trivial task to simultaneously maintain SNM, WAM, and Iread in multi-port bitcells [11].…”

Section: Introductionmentioning

confidence: 99%

A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead

Singh

Aswar

Mohanty

et al. 2010

2010 11th International Symposium on Quality Electronic Design (ISQED)

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Low power, minimum transistor count and fast access static random access memory (SRAM) is essential for embedded multimedia and communication applications realized using system on a chip (SoC) technology. Hence, simultaneous or parallel read/write (R/W) access multi-port SRAM bitcells are widely employed in such embedded systems. In this paper, we present a 2-port 6T SRAM bitcell with multi-port capabilities and a reduced area overhead compared to existing 2-port 7-transistor (7T) and 8T SRAM bitcells. The proposed 2-port bitcell has six transistors (6T) and single-ended read and write bitlines (RBL/WBL). We compare the stability, simultaneous read/write disturbance, SNM sensitivity and misread current from the read bitline with the 7T and 8T bitcells. The static noise margin (SNM) of the 6T bitcells around the write disturbed bitcell is 53% to 61% higher than that of the 7T bitcell. The average active power dissipation under the different read/write operations of the 6T bitcells is 28% lower than the 8T and equal to 7T bitcell. Hence, the proposed 2-port 6T-SRAM is a potential candidate in terms of process variability, stability, area, and power dissipation.

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Horiguchi¹,

Itoh²

2010

Integrated Circuits and Systems

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A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die

Cited by 14 publications

References 19 publications

Robust SRAM Designs and Analysis

Robust SRAM Designs and Analysis

A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead

Redundancy

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