A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead

Abstract

Low power, minimum transistor count and fast access static random access memory (SRAM) is essential for embedded multimedia and communication applications realized using system on a chip (SoC) technology. Hence, simultaneous or parallel read/write (R/W) access multi-port SRAM bitcells are widely employed in such embedded systems. In this paper, we present a 2-port 6T SRAM bitcell with multi-port capabilities and a reduced area overhead compared to existing 2-port 7-transistor (7T) and 8T SRAM bitcells. The proposed 2-port bitcell has six transistors (6T) and single-ended read and write bitlines (RBL/WBL). We compare the stability, simultaneous read/write disturbance, SNM sensitivity and misread current from the read bitline with the 7T and 8T bitcells. The static noise margin (SNM) of the 6T bitcells around the write disturbed bitcell is 53% to 61% higher than that of the 7T bitcell. The average active power dissipation under the different read/write operations of the 6T bitcells is 28% lower than the 8T and equal to 7T bitcell. Hence, the proposed 2-port 6T-SRAM is a potential candidate in terms of process variability, stability, area, and power dissipation.

Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications

“…Also, Table 4 shows read delay of different SRAM cells. The read delay was calculated when the Read-Line or Word-Line rose to 0.5 Â V DD to a time when the output of the sense amplifier is reached to 0.5 Â V DD [31]. In Table 4, we do not consider the write delays.…”

“…18. The read delay was calculated when the Read-Line or Word-Line rose to 0.5 Â V DD to a time when the output of the sense amplifier reached 0.5 Â V DD [31]. In these simulations, the HSPICE parameters were obtained from the latest Predictive Technology Models (PTMs) for the 22-nm technology node [12].…”

Multi-port FinFET SRAM design

“…In Figure 4(c), an extra write assist transistor MN4 is added as a switch, which turns off the feedback loop when writing '1'. The extra transistor is shared through a whole row, reducing the area [8]. Cell stability: Since read ports are isolated, the retention SNM and the two-read SNM are the same, regardless of the change in N fin of the other transistors other than the read port transistors.…”

“…For read operations, as the number of access transistors increases, the read time increases when serving several reads simultaneously, and the internal nodes suffer from the destructive read. To address these issues, single-ended SRAM with isolated read ports has been proposed, where the destructive read is eliminated and read time is reduced [8]. For write operation, one bit line can be eliminated, thus reducing the area and wires in single-ended multi-port SRAM designs.…”

Design of low-leakage multi-port SRAM for register file in graphics processing unit

“…There are many low-power design techniques proposed for SRAM designs [4][5][6][7][8][9]. In this paper, we will examine the efficiency of these low power designs and apply them to the design of the multi-port SRAM for the register file used in a vertex shader processor which is targeting for execution of OpenGL ES 2.0 graphics API [10].…”