Design of low-leakage multi-port SRAM for register file in graphics processing unit

Abstract

This paper combines several low-leakage and lowcost techniques to design multi-port static random access memory (SRAM) for register file in a vertex shader processor for OpenGL ES 2.0 graphics applications. First, precharge control is employed to eliminate unnecessary precharge operations. Then, dynamic forward body-bias control for leakage reduction is proposed to adjust the threshold voltage of transistors depending on whether memory cell is accessed or idle. Different powergating methods are presented for SRAM cells and for sense amplifiers. The thin-cell-like lithography-friendly layout style is adopted for the multi-port SRAM cell to achieve more compact and flexible layout with easy addition of read ports. The crosscoupled inverters in the SRAM cell have asymmetric design to reduce area and also increase the writability. A 32x128-bit register file supporting 5-read and 1-write operations is implemented and verified, which has smaller area and lower leakage compared with that from ARM register file generator.

Efficient Implementation of Many-Ported Memories by Using Standard-Cell Memory Approach

“…To evaluate the effectiveness of our controlled placement methodology, we chose two many-ported memory examples for implementation and comparison with the conventional RTL approach, as well as with other multi-ported memories reported in the literature [3], [28], [35], [36]. The first benchmark circuit -on the low-end of the multi-ported spectrum -is a 32 × 32-bit 3-write 5-read (3W5R) memory block, used as the register file (RF) of a dual-issue RISC-V processor 1 [14].…”

“…The tightly-controlled and guided macros excel in almost every metric. In particular, when comparing the proposed 3W5R register file against existing designs with fewer than 10 ports [3], [35], [36], we can observe that, owing to the efficient allocation of the SCMs, the proposed design leads to the best alternative in terms of power consumption, while offering competitive operating frequency. Furthermore, in contrast to a published many-ported register file [28], the proposed implementation methodology for the 20W/20R register file provides outstanding power savings (several ordersof-magnitude) at the cost of reduced frequency.…”

“…Embedded memories with multiple read/write (R/W) ports are very appealing for modern SoCs [1], [2], [16], [17]. Various blocks that are usually integrated in these systems, such as media and graphics processing units (GPUs) as well as computational cores, require multi-port memories to support instruction-level parallelism with the goal of increasing processing speed while avoiding data serialization and reducing wait states during pipelining [2], [3], [18], [19]. As an example, dual-port memories are widely used for video processing units, since two read and write access operations can be performed within the same clock cycle [20]- [24].…”

“…As an example, dual-port memories are widely used for video processing units, since two read and write access operations can be performed within the same clock cycle [20]- [24]. An even larger number of read ports is also utilized in graphics processors, digital signal processors, and for shared system level memories that provide simultaneous access to multiple processing units [3], [16], [25]- [27]. In addition, a large number of write ports can be useful in multi-threaded applications and vector processing.…”

DRC2: Dynamically Reconfigurable Computing Circuit based on memory architecture

“…The well-known Graphical Processing Units (GPU) are a good example of computing circuits using a register-heavy memory hierarchy (few Mb of register files compared to few Kb in a mainstream CPU) including a very large number of registers files (RF), which allow highly-parallel computing. Moreover, the architecture of SRAM-based RFs itself is also optimized and multi-port bitcells are introduced offering simultaneous read (RD) and write (WR) operations [3][4] to further increase the computing speed. However, parallelization of many computing units and the resulting high throughput of the data leads to a high power consumption [5].…”