A 65 nm standard cell library for ultra low-power applications

Vohrmann, Marten; Saikat, Chatterjee; Lütkemeier, Sven; Jungeblut, Thorsten; Porrmann, Mario; Rückert, Ulrich

doi:10.1109/ecctd.2015.7300041

Cited by 7 publications

(3 citation statements)

References 15 publications

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“…Vth n4 V id − Vth n2 (30) and thus the differential voltage accumulated during the preamplification phase when the input common mode voltage is equal to V DD can be derived as:…”

Section: ) Preamplification Phasementioning

confidence: 99%

“…This approach can either emulate the behavior of analog building blocks or implement analog functions within the digital domain [28]. The adoption of standard-cell-based analog functions enhances design portability across different tech-nologies and allows for the reconfiguration of speed versus supply voltage [29], [30]. This standard-cell-based approach is particularly well-suited for ultra-low voltage (ULV) scenarios, where the stacking of multiple devices becomes challenging, thereby limiting the feasibility of traditional analog design techniques like cascoding.…”

Section: Introductionmentioning

confidence: 99%

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Rail to Rail ICMR and High Performance ULV Standard-Cell-Based Comparator for Biomedical and IoT Applications

Sala,

Centurelli,

Scotti

et al. 2024

IEEE Access

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In this paper a novel ultra-low voltage (ULV) standard-cell-based comparator which provides rail-to-rail input common-mode range (ICMR) is presented. The topology, unlike the others in the literature, uses only 2-inputs NAND gates and is able to operate with supply voltages as low as 0.15V. A detailed theoretical analysis based on transistor level modeling is provided to explain the operating principle and highlight the performance advantages of the proposed comparator. The circuit has been tested through several simulations, including corner analysis and Monte Carlo runs, by using three different technologies: 180 nm, 130 nm and 28 nm for both a supply voltage of 0.3 V and 0.15 V. The results found not only confirm the robustness of the proposed comparator, but also demonstrate very advantageous performances. Indeed, for the same technology node it exhibits the highest speed and the lowest EDP (about ten times lower than the one of the others standard-cell-based comparators in the literature). It exhibits also the lowest power consumption and silicon area.

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“…Vth n4 V id − Vth n2 (30) and thus the differential voltage accumulated during the preamplification phase when the input common mode voltage is equal to V DD can be derived as:…”

Section: ) Preamplification Phasementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Rail to Rail ICMR and High Performance ULV Standard-Cell-Based Comparator for Biomedical and IoT Applications

Sala,

Centurelli,

Scotti

et al. 2024

IEEE Access

View full text Add to dashboard Cite

show abstract

“…This chip consumes about 100 mW at an operating clock frequency of 300 MHz. Additionally, a RISC-like ultra low power CPU, the CoreVA-ULP, is build using a custom standard cell library optimized for sub-threshold operation [24], [25]. Operation voltage range from 1.2 V down to 200 mV and frequency from 94 MHz down to 10 kHz.…”

Section: A Cpu Corementioning

confidence: 99%

CoreVA-MPSoC: A Many-Core Architecture with Tightly Coupled Shared and Local Data Memories

Sievers²,

Daberkow

et al. 2018

IEEE Trans. Parallel Distrib. Syst.

Self Cite

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Abstract-MPSoCs with hierarchical communication infrastructures are promising architectures for low power embedded systems. Multiple CPU clusters are coupled using an Network-onChip (NoC). Our CoreVA-MPSoC targets streaming applications in embedded systems, like signal and video processing. In this work we introduce a tightly coupled shared data memory to each CPU cluster, which can be accessed by all CPUs of a cluster and the NoC with low latency. The main focus is the comparison of different memory architectures and their connection to the NoC. We analyze memory architectures with local data memory only, shared data memory only, and a hybrid architecture integrating both. Implementation results are presented for a 28 nm FD-SOI standard cell technology. A CPU cluster with shared memory shows similar area requirements compared to the local memory architecture. We use post place and route simulations for precise analysis of energy consumption on both cluster and NoC level using the different memory architectures. An architecture with shared data memory shows best performance results in combination with a high resource efficiency. On average, the use of shared memory shows a 17.2% higher throughput for a benchmark suite of 10 applications compared to the use of local memory only. the communication infrastructure goes the on-chip memory architecture, which also has a huge impact on performance and energy efficiency. The main focus of this paper is the comparison of different memory architectures and their interaction with the NoC for many core systems. Compared to traditional processor systems, lots of many cores feature a different memory management, which changes the requirements on memory and NoC infrastructure. Traditional processor systems use a memory hierarchy with several (private and shared) on-chip caches, external DRAM, and a unified address space. This allows for easy programming, but results in unpredictable memory access times. Additionally, the cache logic and the coherence handling require a high amount of chip area and power. Therefore, a lot of Many-Core systems omit data caches and use software-managed scratchpad memories instead, which provide a resource-efficient alternative [1]. For performance reasons, the scratchpad memories are tightly attached to each CPU and communication between CPUs is initiated by software. In [2] we showed that area and power consumption of a single CoreVA CPU's data memory increases by 10%, when using a cache instead of scratchpad memory. Due to cache coherence issues it can be expected that these values will even increase for a cache-based many core system. Additionally, software-managed scratchpad memories gives full control of data communication to the programmer or an automatic partitioning tool (cf. Section III-E) and allows for a more accurate performance estimation.The many core architecture considered in this work is our CoreVA-MPSoC, which targets streaming applications in embedded and energy-limited systems. Examples for streaming applications are signal pr...

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Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology

Vohrmann

Geisler

Jungeblut

et al. 2017

2017 European Conference on Circuit Theory and Design (ECCTD)

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A 65 nm standard cell library for ultra low-power applications

Cited by 7 publications

References 15 publications

Rail to Rail ICMR and High Performance ULV Standard-Cell-Based Comparator for Biomedical and IoT Applications

Rail to Rail ICMR and High Performance ULV Standard-Cell-Based Comparator for Biomedical and IoT Applications

CoreVA-MPSoC: A Many-Core Architecture with Tightly Coupled Shared and Local Data Memories

Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology

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