A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell

Line width optimization for interdigitated power/ground networks

“…In this paper, however, the skin effect is neglected since the highest target frequency is 10 GHz, resulting in a skin depth of 0.65 µm for copper wires. Half the thickness of the highest metal layer for a 65 nm CMOS technology [17] is less than the skin depth, justifying the assumption of a uniform current distribution. In addition, with advancements in technology, the thickness of the metal layers is decreasing, making the skin effect less significant.…”

“…3. A 1 x 1 mm 2 area of the top metal layer for a 65 nm CMOS [17] technology is chosen. The target frequency is 5 GHz.…”

On-Line Failure Detection and Confinement in Caches

“…ROM cells require a single bitline given that they are connected directly to Vcc/Vss, and hence their read speed is very high (differential signaling is not required). ROM cells require much smaller area than conventional 6-T SRAM cells [3,13]. Therefore, bitlines, Vcc and Vss wires could be laid out in a more compressed manner for ROM cells than for SRAM cells.…”

“…Since CACTI does not model ROM cells needed for wordline signatures, we model them as SRAM cells. We have incorporated ROM cells based on regular SRAM cell designs [3,13], where bitlines are interleaved with Vcc and Vss lines as shown in Figure 2. ROM cells require a single bitline given that they are connected directly to Vcc/Vss, and hence their read speed is very high (differential signaling is not required).…”

“…Such failures are likely to appear in highly integrated memories [3], and the failure rate is expected to worsen in future technologies. Thus, techniques to detect and correct failures in the field become a must.…”