A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs

Jeon, Young‐Jin; Lee, Joong-Ho; Jin, Kyo-Won; Min, Kyeong‐Sik; Chung, Jayong; Park, H.-J.

doi:10.1109/jssc.2004.835809

Cited by 34 publications

(2 citation statements)

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“…In order to achieve a memory bus data rate of over 400 Mbps/pin, DDR-x SDRAMs must incorporate an on-chip delay-locked loop (DLL) [1,2,3,4,5,6,7,8,9,10,11,12] that can eliminate skew problems and achieve higher timing margin at high frequencies. To design a DLL that can support both DDR3 and DDR4 specifications at the same time [13,14], the DLL should be locked within 512 clock cycles and operate over a frequency range from 300 MHz to 1.6 GHz using an internal supply voltage of less than 1.2 V. Also, the DLL must be capable of correcting the duty cycle of the distorted input clock so that the data-valid window (tDV) could be widened [2].…”

Section: Introductionmentioning

confidence: 99%

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A fast-locking harmonic-free digital DLL for DDR3 and DDR4 SDRAMs

Yoon

Heo

Kim

2017

IEICE Electron. Express

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A new digital delay-locked loop (DLL) for DDR3/DDR4 SDRAM is presented. The proposed digital DLL employs a new noisetolerant triple (MSB-interval + binary + sequential) search algorithm for implementing a harmonic-free, fast-locking capability while retaining low jitter, low power performance, and a wide operating frequency range. The proposed DLL with duty-cycle correction is designed using a 38-nm CMOS process and occupies an active area of just 0.02 mm 2 . The DLL operates over a frequency range of 0.3-2.0 GHz and achieves a peak-to-peak jitter of 7.78 ps and dissipates 3.48 mW from a 1.1 V supply at 1 GHz.

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Section: Introductionmentioning

confidence: 99%

“…Currently, most DDR3/DDR4 SDRAMs use a digital DLL [1,2,3,4,10,11]. One of the reasons for using digital architectures is because DDR3/DDR4 SDRAMs require fast recovery times for various power mode transitions.…”

Section: Introductionmentioning

confidence: 99%