A 66-400 MHz, adaptive-lock-mode DLL circuit with duty-cycle error correction [for SDRAMs]

Okuda, Yukihiko; Horiguchi, Masashi; Nakagome, Y.

doi:10.1109/vlsic.2001.934188

Cited by 5 publications

(4 citation statements)

References 1 publication

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“…Equation (1) shows that the DLL is prone to the false locking problem when process variations are taken into account [7]. Therefore, some solutions [6]- [10] are proposed to overcome this problem. They are described as follows.…”

Section: Range Problem Of Conventional Dllsmentioning

confidence: 99%

A WideRange DelayLocked Loop with a Fixed Latency of One Clock Cycle

Razavi¹

2009

Phase-Locking in High-Performance Systems

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A delay-locked loop (DLL) with wide-range operation and fixed latency of one clock cycle is proposed. This DLL uses a phase selection circuit and a start-controlled circuit to enlarge the operating frequency range and eliminate harmonic locking problems. Theoretically, the operating frequency range of the DLL can be from 1 ( max ) to 1 (3 min ), where min and max are the minimum and maximum delay of a delay cell, respectively, and is the number of delay cells used in the delay line. Fabricated in a 0.35-m single-poly triple-metal CMOS process, the measurement results show that the proposed DLL can operate from 6 to 130 MHz, and the total delay time between input and output of this DLL is just one clock cycle. From the entire operating frequency range, the maximum rms jitter does not exceed 25 ps. The DLL occupies an active area of 880 m 515 m and consumes a maximum power of 132 mW at 130 MHz.

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Section: Range Problem Of Conventional Dllsmentioning

confidence: 99%

A WideRange DelayLocked Loop with a Fixed Latency of One Clock Cycle

Razavi¹

2009

Phase-Locking in High-Performance Systems

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“…Equation 1shows that the DLL is prone to the false locking problem when process variations are taken into account [7]. Therefore, some solutions [6]- [10] are proposed to overcome this problem. They are described as follows.…”

Section: Andmentioning

confidence: 99%

“…The DLL developed in [9] uses a stage selector for fast-locked and wide-range operations, but the DLL requires an additional VCDL, which increases the area. A similar DLL can automatically change its lock mode to extend the operation range, but the latency of the DLL will be larger than one clock cycle [10].…”

Section: Andmentioning

confidence: 99%

A wide-range delay-locked loop with a fixed latency of one clock cycle

Chang

Lin

Yang

et al. 2002

IEEE J. Solid-State Circuits

138

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A delay-locked loop (DLL) with wide-range operation and fixed latency of one clock cycle is proposed. This DLL uses a phase selection circuit and a start-controlled circuit to enlarge the operating frequency range and eliminate harmonic locking problems. Theoretically, the operating frequency range of the DLL can be from 1 (max) to 1 (3 min), where min and max are the minimum and maximum delay of a delay cell, respectively, and is the number of delay cells used in the delay line. Fabricated in a 0.35-m single-poly triple-metal CMOS process, the measurement results show that the proposed DLL can operate from 6 to 130 MHz, and the total delay time between input and output of this DLL is just one clock cycle. From the entire operating frequency range, the maximum rms jitter does not exceed 25 ps. The DLL occupies an active area of 880 m 515 m and consumes a maximum power of 132 mW at 130 MHz.

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“…Jang et al 2 and Okuda et al 3 describe methods for correcting errors in duty cycle for high-speed chips. Chen et al 4 fabricated high dielectric constant film and studied dynamic stressing characteristics related to frequency and duty cycle.…”

Section: Introductionmentioning

confidence: 99%

On-board SRAM signal density stress prediction

Hsieh

Sharma

2006

SPIE Proceedings

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Static Random Access Memory (SRAM) chips undergo several types of stress in the field. Existing work has concentrated primarily on humidity and thermal stress; there has been relatively little emphasis on signal density stress prediction. Objectives of this study were to (1) explore the impact of signal density stress on SRAM functionality, (2) observe thermal profile differences under signal density stress over time, (3) predict stress levels using artificial neural network models, and (4) develop a generic methodology for signal density stress prediction. An 8051 programming board containing an SRAM chip was used. Two kinds of signal density stress were investigated-varying the content written to memory, and varying signal frequency in accessing SRAM through flash memory. Preliminary experiments suggest that both types of stress impact the SRAM thermal profile. Thermal profile data were used to build back propagation neural network models; 70% of the data was used to build the models and 30% was used for testing. Various neural network training functions and topologies were used to predict chip stress level given thermal profile data. Data from both the die area and the entire chip were used. For both types of stress, using data from the die area in a network with a 3-3-1 topology yielded the lowest average error rate-1.3% for data content stress level prediction and 7.6 % for signal frequency stress level prediction. The trainRP function resulted in a lower error rate than other training functions that were evaluated.

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A 66-400 MHz, adaptive-lock-mode DLL circuit with duty-cycle error correction [for SDRAMs]

Cited by 5 publications

References 1 publication

A WideRange DelayLocked Loop with a Fixed Latency of One Clock Cycle

A WideRange DelayLocked Loop with a Fixed Latency of One Clock Cycle

A wide-range delay-locked loop with a fixed latency of one clock cycle

On-board SRAM signal density stress prediction

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