A 6GS/s 0.5GHz BW continuous-time 2-1-1 MASH ΔΣ modulator with phase-boosted current-mode ELD compensation in 40nm CMOS

Zhang, C.; Breems, Lucien J.; Liu, Q.; Radulov, Georgi; Bolatkale, Muhammed; Bajoria, Shagun; Rutten, R. J.; Roermund, Arthur van

doi:10.1109/esscirc53450.2021.9567777

Cited by 6 publications

(2 citation statements)

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“…Therefore, the noise and mismatch errors of the iDAC are only marginally suppressed. To tackle all these issues, extra noise budgeting, proper device sizing and analog/digital correction have to be introduced at the cost of power efficiency and design complexity [33]. It was mentioned in the previous section that the interstage DAC is not needed for replication of the quantization error, but for signal cancellation.…”

Section: A Ct Mash Residue Generationmentioning

confidence: 99%

High-Speed and High-Performance Continuous-Time ADCs for Automotive Receivers

Breems,

Bolatkale,

Liu

et al. 2023

IEEE Open J. Solid-State Circuits Soc.

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This paper presents an overview of high-speed and high-performance continuous-time ADCs with a special attention to the application field of automotive receivers for broadcast radio and radar. An overview of the continuous-time ADC architectural space is presented and the key design challenges related to high linearity and broadband signal conversion are described. Insights are given in the architectural and design choices to accomplish high-end performance points. A selection of case studies is presented that achieve state-of-the-art performance metrics with respect to linearity, bandwidth and power efficiency.

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Section: A Ct Mash Residue Generationmentioning

confidence: 99%

High-Speed and High-Performance Continuous-Time ADCs for Automotive Receivers

Breems,

Bolatkale,

Liu

et al. 2023

IEEE Open J. Solid-State Circuits Soc.

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“…SAR and pipelined ADCs were typically used in these scenarios because they offer a good compromise between resolution and speed. Compared to classical Nyquist converters, CT

ADCs have been investigated and drastically improved towards high conversion rates [ 2 ]. Due to their implicit anti-aliasing filtering (AAF), robustness to interference, and resistive input impedance, they have achieved a dominant position for digitization in wireless transceivers [ 3 ].…”

Section: Introductionmentioning

confidence: 99%

A 40 MHz 11-Bit ENOB Delta Sigma ADC for Communication and Acquisition Systems

Fakhoury

Jabbour

Nguyen

2022

Sensors

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This paper describes a Delta Sigma ADC IC that embeds a 5th-order Continuous-Time Delta Sigma modulator with 40 MHz signal bandwidth, a low ripple 20 to 80 MS/s variable-rate digital decimation filter, a bandgap voltage reference, and high-speed CML buffers on a single die. The ADC also integrates on-chip calibrations for RC time-constant variation and quantizer offset. The chip was fabricated in a 1P7M 65 nm CMOS process. Clocked at 640 MHz, the Continuous-Time Delta Sigma modulator achieves 11-bit ENOB and 76.5 dBc THD up to 40 MHz of signal bandwidth while consuming 82.3 mW.

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