A 7.4-to-14GHz PLL with 54fs&lt;inf&gt;rms&lt;/inf&gt; jitter in 16nm FinFET for integrated RF-data-converter SoCs

Turker, Didem; Bekele, Ade; Upadhyaya, Parag; Verbruggen, Bob; Cao, Ying; Ma, Shunchao; Erdmann, Christophe; Farley, Brendan; Frans, Yohan; Chang, Ken

doi:10.1109/isscc.2018.8310342

Cited by 45 publications

(11 citation statements)

References 2 publications

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“…Thus, the non-ideal switches effects should be considered in the circuit design, such as clock feedthrough and charge sharing. To overcome the lack of charge sharing among the parasitic capacitances at the current sources' drain nodes dp, dn and the capacitors in the LF, a current-steering topology [26,27,30] is adopted using transistors M13-M16 as switches-at-drain with operational amplifier, where and are either connected to or dumped to . The operational amplifier OP3 which is served as the unity-gain feedback buffer is used to keep the output common mode constant during CP switching.…”

Section: Conventional Charge Pumpmentioning

confidence: 99%

“…However, the value of these resistors is easily affected by multiple factors. In addition, a common-mode feedback scheme [4], an active feedback circuit [26,27,28] and a gate bias technique [29] compensate the current mismatch based on the operational amplifier or the bulk driven cascode current mirror, but the reduction of the output dynamic voltage range is still inevitable in these methods.…”

Section: Introductionmentioning

confidence: 99%

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A high swing charge pump with current mismatch reduction for PLL applications

Chen

Han

Wang

2021

IEICE Electron. Express

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A charge pump (CP) is widely used in modern phase-locked loop (PLL) implementations. The CP current mismatch is a dominant source of static phase offset and reference spur in the PLL output signals. In this paper, a novel CP with small current mismatch characteristic over a wide output voltage range is proposed. The specially designed dual compensation circuits use the unity-gain feedback operational amplifier and current mirrors to reduce the current mismatch when the output voltage is closed to the supply voltage (V DD) or ground (GND). And the additional feedback transistors are used to reduce the impact from the channel length modulation effect. Post-layout simulation results demonstrate that the output current of the proposed CP in a 40 nm CMOS technology is 115 μA. Moreover, the current mismatch is less than 0.97 μA or 0.84% over the output voltage range from 0.04 to 1.07 V covering more than 93.6% of the 1.1 V supply. Thus, the proposed CP maximizes the dynamic range, and reduces the phase offset and reference spur of CP-PLLs.

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Section: Conventional Charge Pumpmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A high swing charge pump with current mismatch reduction for PLL applications

Chen

Han

Wang

2021

IEICE Electron. Express

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“…This limitation makes it difficult to realize a low-jitter frequency synthesizer with a low f REF source [2]. Thus, a high f REF source is more popular than a lower one [10]- [12] in ultra-low-jitter PLL applications.…”

Section: Introductionmentioning

confidence: 99%

A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth

Qiu

Sun

Liu

et al. 2021

IEEE J. Solid-State Circuits

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In this article, a mixed-signal, 32-kHz referencebased 2.4-GHz fractional-N over-sampling phase-locked loop (OSPLL) is proposed. Different from the conventional 1× sampling PLL, which only uses zero-crossing timing information of the reference signal, the proposed OSPLL fully utilizes both the voltage and timing domain information of the reference signal and realizes oversampling ratio (OSR) times phase detection (PD) in one reference cycle. The proposed OSPLL employs the digitalto-analog converter (DAC) to construct the reference-like feedback signal in the voltage domain and utilizes the digital-to-time converter (DTC) to improve PD resolution in the time domain. The adaptive lookup table (LuT)-based calibration is proposed to generate the correct information for DAC and DTC control. A clocked passive comparator works as a bang-bang phase detector (BBPD) for the PLL control and LuTs' construction. The co-design of low-noise analog circuits and digital calibrations enables good jitter and spur performance. The proposed OSPLL is fabricated in 65-nm CMOS technology, with the core area of 0.58 mm 2 , and the power consumption is 4.97 mW with a 1-V power supply. It achieves 5.79-ps root-mean-square (rms) jitter in fractional-N modes with the loop-bandwidth (BW loop ) of 200 kHz, corresponding to the figures of merit (FoMs) of −217.8 dB. The measured fractional spur is less than −36 dBc, and the reference spur is −78 dBc, respectively.

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“…In a classical charge pump PLL (CPPLL) system [9][10][11][12][13][14][15], phase noise is mainly generated from two parts: out-of-band noise which is dominated by the voltage-controlled oscillator (VCO) (noise of low pass filter is neglected); and in-band noise which is dominated by the phase detector, charge pump and divider. Several efforts have been addressed to study the phase noise of VCOs [16][17][18] and designs with ultra-low power consumption have been published [19][20][21].…”

Section: Introductionmentioning

confidence: 99%

A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fsrms Integrated Jitter and −251.6 dB FoM

Zuo

Zhao

Zhou

2021

Sensors

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This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to avoid the degraded feature caused by the decreasing of the supply voltage. The I-path is built by a rail-to-rail SSCP to suppress the phase noise of the voltage-controlled oscillator (VCO) and avoid the trouble of locking at the non-zero phase offset (as in type-I PLL). The proposed design is implemented in a 40-nm CMOS process. The measured output frequency range is from 5.3 to 5.9 GHz with 196.5 fs root mean square (RMS) integrated jitter and −251.6 dB FoM.

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A 7.4-to-14GHz PLL with 54fs<inf>rms</inf> jitter in 16nm FinFET for integrated RF-data-converter SoCs

Cited by 45 publications

References 2 publications

A high swing charge pump with current mismatch reduction for PLL applications

A high swing charge pump with current mismatch reduction for PLL applications

A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth

A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fsrms Integrated Jitter and −251.6 dB FoM

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