A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing

Lin, Mu-Shan; Huang, Tze-Chiang; Tsai, Chien‐Hsiung; Tam, King-Ho; Hsieh, Kenny; Chen, Ching-Fang; Huang, Wen-Hung; Hu, Chi-Wei; Chen, Yuchi; Goel, Sandeep; Fu, Chin-Ming; Rusu, Stefan; Li, Chao-Chieh; Yang, Shixuan; Wong, Mei; Yang, Shuo; Lee, Frank

doi:10.1109/jssc.2019.2960207

Cited by 59 publications

(19 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In the Chiplet-based computing system, the Chiplet is prepared with the optimized technology and further integrated with 2.5/3D advanced packing technology, which has high bandwidth and energy efficiency and low data delay. As shown in Table 1, in [22], the computing architecture was constructed with the four Chiplets using 2.5D Chip on Wafer on a substrate (CoWoS) technology, and the bandwidth can be improved to 1.6 Tb/s/mm 2 in high-performance computing. In [24], the delay of Agilex can be reduced to 60 ps by using 2.5D integration technology, and the architecture has high configurability and reusability.…”

Section: Discussionmentioning

confidence: 99%

“…The system can achieve a bandwidth of 3 TB/s and power consumption of 160 W at 1 GHz. Lin et al [22] designed a Chiplet-based high-performance computing architecture, which integrates four 7 nm ARM Cortex-A72 cores in two computing Chiplets. The Chiplet communication can be achieved through the parallel channels formed by Low-voltage-InPackage-INterCONnect technology.…”

Section: Computing Architecture Integrated With 25d Technologymentioning

confidence: 99%

See 1 more Smart Citation

Architecture of Computing System based on Chiplet

et al. 2022

View full text Add to dashboard Cite

Computing systems are widely used in medical diagnosis, climate prediction, autonomous vehicles, etc. As the key part of electronics, the performance of computing systems is crucial in the intellectualization of the equipment. The conflict between performance, efficiency, and cost can be solved by choosing an appropriate computing system architecture. In order to provide useful advice and instructions for the designers to fabricate high-performance computing systems, this paper reviews the Chiplet-based computing system architectures, including computing architecture and memory architecture. Firstly, the computing architecture used for high-performance computing, mobile, and PC is presented and summarized. Secondly, the memory architecture based on mainstream memory and emerging non-volatile memory used for data storing and processing are introduced, and the key parameters of memory are compared and discussed. Finally, this paper is concluded, and the future perspectives of computing system architecture based on Chiplet are presented.

show abstract

Section: Discussionmentioning

confidence: 99%

Section: Computing Architecture Integrated With 25d Technologymentioning

confidence: 99%

Architecture of Computing System based on Chiplet

et al. 2022

View full text Add to dashboard Cite

show abstract

“…LIPINCON [25] is a high-performance interconnect interface proposed by TSMC for chiplets. By using advanced silicon-based interconnect packaging technologies (such as InFO and CoWoS) and timing compensation technology, LIPINCON could reduce power consumption and area overhead without PLL/DLL.…”

Section: Vsr Serdesmentioning

confidence: 99%

Chiplet Heterogeneous Integration Technology—Status and Challenges

Hou²,

et al. 2020

View full text Add to dashboard Cite

As a heterogeneous integration technology, the chiplet-based design technology integrates multiple heterogeneous dies of diverse functional circuit blocks into a single chip by using advanced packaging technology, which is a promising way to tackle the failure of Moore’s law and Dennard scaling. Currently, as process nodes move forward, dramatically rising cost, design cycle, and complexity are driving industry to focus on the chiplets. Chiplets allows IC designers to merge dies fabricated at different process nodes and reuse them in different projects, which helps to reduce the cost during design and improve yield. In this review, we look back at the industry’s efforts over the past decade and summary the concepts and techniques associated with chiplets. In the end, a discussion and conclusion will be given to forecast the future of chiplets.

show abstract

“…At the same time, the typical gains in energy-efficiency that dimensional scaling has brought over the past several decades are slowing down [6] [7] [8]. 2D enhanced architectures [9] place dies side-by-side and interconnect them through mediums such as a silicon interposer [10], or embedded bridge [11] [12] to achieve higher interconnect densities compared to mainstream packages. 3D architectures like hybrid wafer bonding [13] [14] directly stack two or more dies on top of each other without using the agency of the package, This manuscript was submitted for review on 04/28/2021.…”

Section: Introductionmentioning

confidence: 99%

Thermal-Aware Design Space Exploration of 3-D Systolic ML Accelerators

Mathur

Kumar

John

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

View full text Add to dashboard Cite

ML accelerators have a broad spectrum of usecases that pose different requirements on accelerator design for latency, energy, and area. In the case of systolic array-based ML accelerators, this puts different constraints on Processing Element (PE) array dimensions and SRAM buffer sizes. 3D integration packs more compute or memory in the same 2D footprint, which can be utilized to build more powerful or energyefficient accelerators. However, 3D also expands the design space of ML accelerators by additionally including different possible ways of partitioning the PE array and SRAM buffers among the vertical tiers. Moreover, the partitioning approach may also have different thermal implications. This work provides a systematic framework for performing system-level design space exploration of 3D systolic accelerators. Using this framework, different 3D-partitioned accelerator configurations are proposed and evaluated. The 3D-stacked accelerator designs are modeled using hybrid wafer bonding technique with a 1.44 µm pitch of 3D connection. Results show that different partitioning of the systolic array and SRAM buffers in a 4-tier 3D configuration can lead to either 1.1-3.9X latency reduction or 1-3X energy reduction compared to the baseline design of the same 2D area footprint. It is also shown that by carefully organizing the systolic array and SRAM tiers using logic over memory, the temperature rise with 3D across benchmarks can be limited to 6°C.

show abstract

A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing

Cited by 59 publications

References 4 publications

Architecture of Computing System based on Chiplet

Architecture of Computing System based on Chiplet

Chiplet Heterogeneous Integration Technology—Status and Challenges

Thermal-Aware Design Space Exploration of 3-D Systolic ML Accelerators

Contact Info

Product

Resources

About