A 72 dB-DR 465 MHz-BW Continuous-Time 1-2 MASH ADC in 28 nm CMOS

Dong, Yang; Zhao, Ji; Yang, Wenhua; Caldwell, Trevor; Shibata, Hajime; Zhao, Li; Schreier, Richard; Meng, Qingdong; Silva, Jose B.; Paterson, Donald; Gealow, Jeffrey

doi:10.1109/jssc.2016.2587881

Cited by 53 publications

(23 citation statements)

References 15 publications

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“…• a seventh-order of more than 45 dB DC gain and a f u of 15 GHz in 65 nm CMOS [1], • a fifth-order of approximately 49 dB DC gain and a f u of 6.7 GHz in 28nm CMOS [12], • a fourth-order with DC gain of 84.3 dB and a f u of 1.19 GHz in 40 nm CMOS [6], • a third-order of 30 dB DC gain and a f u of 8.6 GHz in 28nm CMOS [13], or • a second-order of 46 dB DC gain and a f u of 7.8 GHz in 40 nm CMOS [14].…”

Section: Introductionmentioning

confidence: 99%

A g_m/I_D Methodology Based Data-Driven Search Algorithm for the Design of Multistage Multipath Feed-Forward-Compensated Amplifiers Targeting High Speed Continuous-Time ΣΔ-Modulators

Gebreyohannes

Porte

Louërat

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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This work presents a methodology for sizing transistors of a multi-stage, multi-path capacitor-less feed-forward compensated operational amplifiers employed in advanced CMOS process implementation of continuous-time bandpass Σ∆modulators. The paper describes the methodology: on system level, dealing with the placement of poles and zeros; and on circuit level, discussing issues related to biasing, frequency response and other important performance metrics of the basic diffpair. Algorithms are provided to simplify mathematical aspects of the work. The validity and the limitations of the proposed methodology are further discussed from the single-pole system used to model the individual amplification stages of the multistage amplifier. The worthiness of the proposed methodology in sizing the transistors of complex amplifier structures such as the capacitor-less multi-stage, multi-path feed-forward-compensated amplifiers is demonstrated using two design examples. A 3 rdorder amplifier with a DC gain of 52.6 dB and that reaches a unity-gain frequency of above 14 GHz while consuming only 5.6 mA from a 1 V supply; and a 4 th-order amplifier with DC gain of 73.5 dB that achieves a 25.7 dB gain at 1 GHz while consuming 4.8 mW are designed in 28nm CMOS FDSOI.

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Section: Introductionmentioning

confidence: 99%

A g_m/I_D Methodology Based Data-Driven Search Algorithm for the Design of Multistage Multipath Feed-Forward-Compensated Amplifiers Targeting High Speed Continuous-Time ΣΔ-Modulators

Gebreyohannes

Porte

Louërat

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…However, the requirement of oversampling ratios (OSRs), which is typically over 16 [3][4][5][6] MHz BW have been proposed by using nanoscale CMOS processes, which allow multi-GHz clock rate. Previously, high frequency ADCs usually adopt continuous-time (CT) realizations [3][4][5][6][7][8][9] instead of discrete-time (DT) realizations. The latter is implemented by switched capacitor circuit, and its accuracy relies on capacitor matching, which means a robust operation under process variation is offered.…”

Section: Introductionmentioning

confidence: 99%

“…However, the increased loop filter orders cause power consumption, instability, and design complexity. The multi-stage noiseshaping (MASH) architecture [6,8], implemented by cascaded low-order local modulators without feedback path among each other, was employed to alleviate stability issues but with mismatch sensitiveness. Moreover, a modulator with a multi-bits quantizer gets a conditionally high DR with an exponential increasing comparator amount.…”

Section: Introductionmentioning

confidence: 99%

A 100-Mhz Bandwidth 80-dB Dynamic Range Continuous-Time Delta-Sigma Modulator with a 2.4-Ghz Clock Rate

Xiao

Ren

et al. 2020

Nanoscale Res Lett

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The bandwidth of a modulator is limited by the clock rate due to the oversampling ratio requirement. As the nanoscale CMOS processes are developing rapidly, it is possible to design wide bandwidth and high dynamic range continuous-time modulators for high-frequency applications. This paper proposes a 3rd-order 4-bit continuous-time modulator with a single-loop feedforward topology. This modulator is designed in a 40-nm CMOS process and achieves 80-dB dynamic range and a 100-MHz bandwidth at a clock rate of 2.4 GHz. The modulator consumes 69.7 mW from 1.2 V power supply.

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“…There are several ways to reduce the impact of the mismatch of the DACs in ∆Σ ADCs. The most intuitive way is to size up the cell unit of the DAC, which definitely increases the excess loop delay (ELD) of the closed-loop system, consumes more power and causes a larger dynamic error [4], [10]. Dynamic element matching techniques such as [11] have also been used to achieve high linearity.…”

Section: Introductionmentioning

confidence: 99%

Efficient Offline Outer/Inner DAC Mismatch Calibration in Wideband ΔΣ ADCs

Liu

Rombouts

Gielen

2020

IEEE Trans. Circuits Syst. I

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Distortion due to feedback DAC mismatch is a key limitation in ∆Σ ADCs for wideband wireless communications. This paper presents an efficient frequency-domain mask-based offline mismatch calibration method of both the outer DAC and the inner DACs in a ∆Σ ADC. The test stimulus for the calibration is a two-tone signal near the band edge. To avoid the need for high-performance signal generation, a frequency mask is applied to void the stimulus signal and its phase noise. In this way, the method is robust against distortion and jitter in the stimulus signal, which therefore could be combined from two lowquality signal generators. The two-tone band-edge signal has the additional benefit that the number of needed samples of the excitation signal is very modest because as many intermodulations as possible contribute to the calculation of the mismatch errors of the DACs. Experimental results confirming the calibration method are obtained from a prototype chip, designed for an 85MHz signal bandwidth in 28nm CMOS technology. A two-tone stimulus around 78 MHz is applied to calculate the mismatch of the outer DAC and the inner DAC with only 68K samples. With the DACs calibrated, an SFDR improvement of 28.1 dB is achieved for a single-tone input at 5 MHz, while for a twotone input around 71 MHz, the IM3 is improved from -63.6 dBc to below the noise floor (<-94.1 dBc). This illustrates the effectiveness of the approach.

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A 72 dB-DR 465 MHz-BW Continuous-Time 1-2 MASH ADC in 28 nm CMOS

Cited by 53 publications

References 15 publications

A g_m/I_D Methodology Based Data-Driven Search Algorithm for the Design of Multistage Multipath Feed-Forward-Compensated Amplifiers Targeting High Speed Continuous-Time ΣΔ-Modulators

A g_m/I_D Methodology Based Data-Driven Search Algorithm for the Design of Multistage Multipath Feed-Forward-Compensated Amplifiers Targeting High Speed Continuous-Time ΣΔ-Modulators

A 100-Mhz Bandwidth 80-dB Dynamic Range Continuous-Time Delta-Sigma Modulator with a 2.4-Ghz Clock Rate

Efficient Offline Outer/Inner DAC Mismatch Calibration in Wideband ΔΣ ADCs

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A 72 dB-DR 465 MHz-BW Continuous-Time 1-2 MASH ADC in 28 nm CMOS

Cited by 53 publications

References 15 publications

A gm/ID Methodology Based Data-Driven Search Algorithm for the Design of Multistage Multipath Feed-Forward-Compensated Amplifiers Targeting High Speed Continuous-Time ΣΔ-Modulators

A gm/ID Methodology Based Data-Driven Search Algorithm for the Design of Multistage Multipath Feed-Forward-Compensated Amplifiers Targeting High Speed Continuous-Time ΣΔ-Modulators

A 100-Mhz Bandwidth 80-dB Dynamic Range Continuous-Time Delta-Sigma Modulator with a 2.4-Ghz Clock Rate

Efficient Offline Outer/Inner DAC Mismatch Calibration in Wideband ΔΣ ADCs

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A g_m/I_D Methodology Based Data-Driven Search Algorithm for the Design of Multistage Multipath Feed-Forward-Compensated Amplifiers Targeting High Speed Continuous-Time ΣΔ-Modulators

A g_m/I_D Methodology Based Data-Driven Search Algorithm for the Design of Multistage Multipath Feed-Forward-Compensated Amplifiers Targeting High Speed Continuous-Time ΣΔ-Modulators