A 73&amp;#x03BC;W 400Mbps stress tolerant 1.8V-3.6V driver in 40nm CMOS

Monga, Sushrant; Kumar, Vinod

doi:10.1109/esscirc.2011.6044896

Cited by 6 publications

(2 citation statements)

References 8 publications

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“…The I ON degradation of MOSFET due to HCI and BTI effect is one of the most challenging reliability concerns for Input/Output (I/O) buffer designs in nano-scale CMOS process [6], [7]. The signal integrity [8] and transmission line related issues like overshoot and undershoot [9] accelerate the degradation due to HCI and BTI effect on I/O buffer especially on output driver because it is directly interfacing with the peripheral devices.…”

Section: Introductionmentioning

confidence: 99%

On-chip aging compensation for output driver

Kumar

2014

2014 IEEE International Reliability Physics Symposium

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In this paper an on-chip aging compensation technique for CMOS output driver is proposed. It contains an aging compensation cell which will detect the degradation in the ON current (I ON ) of output driver due to the HCI and BTI effect. Based on the degradation in the I ON the aging compensation cell will generate aging compensation codes AP[0:3] for PMOS driver and AN[0:3] for NMOS driver. These aging compensation codes will increase the drive strength of output driver to compensate the degradation in I ON of output driver due to HCI and BTI effect. The proposed design is implemented in 40nm CMOS process by using 1.8V thick-oxide (32Å) devices. The measurement result shows that by using the proposed aging compensation technique the impact of aging on output driver get reduced by 70% after 10 years of operation.

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Section: Introductionmentioning

confidence: 99%

On-chip aging compensation for output driver

Kumar

2014

2014 IEEE International Reliability Physics Symposium

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“…Unfortunately, such transistors are technology dependent and not available in recently developed processes such as the 28nm TSMC technology. Another way of designing these high-voltage circuits compatible with scaled technologies is to use stacked low-voltage standard CMOS transistors [2]- [11].…”

Section: Introductionmentioning

confidence: 99%

Design of a high-voltage differential amplifier based on stacked low-voltage standard CMOS with different input stages

Pashmineh

Killat

2015

2015 38th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO)

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This paper presents the design of a high-voltage differential amplifier using six different pre-input stage circuits to reduce high-voltage input levels to low-voltage signals. The proposed circuits are designed using 65 nm CMOS process technology with a nominal voltage of 2.5 V and a supply voltage of 5 V. The designs are based on stacked low-voltage standard CMOS transistors. The different pre-input stage circuits are compared to each other in terms of their circuit description, drawbacks, advantages and simulation results. The principle of the five designed pre-input stage circuits can be applied to higher voltage range input signals as well.I.

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Programmable CCCII: reliability analysis and design methodology

Tiwari

Pandey

Paul

et al. 2019

IET Circuits, Devices & Systems

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In this study, an effective and efficient approach for reliability analysis is developed to bridge the gap between devicelevel reliability and that at the product level. Continual reduction of device dimensions, gate-oxide and increase in channel doping results in an increased electric field which is introducing most of the reliability concerns. Four most important reliability issues impacting circuit design are hot carrier injection, bias temperature instability, time-dependent dielectric breakdown and self-heating. As the second-generation current controlled conveyor (CCCII) circuit are used to implement oscillator, filter clock and so on, which are working continuously even in sleep mode. So it is important to take care of all the reliability aspects while designing CCCII. There is a challenge in complex design to identify which devices (MOS, resistor and capacitor) are susceptible to degradation and then redesign and mitigate this effect for a robust and reliable design. The objective of this work is to detect reliability issues and design a programmable current conveyor which can work safely for a long duration. The circuit has been designed and simulated using 28 nm CMOS technology model parameters on Cadence Virtuoso/AMS environment (ELDO simulator) using ± 1.8 V supply voltage and results have been verified with post-layout netlist.

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A 73μW 400Mbps stress tolerant 1.8V-3.6V driver in 40nm CMOS

Cited by 6 publications

References 8 publications

On-chip aging compensation for output driver

On-chip aging compensation for output driver

Design of a high-voltage differential amplifier based on stacked low-voltage standard CMOS with different input stages

Programmable CCCII: reliability analysis and design methodology

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